Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the se...

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Autores principales:	Gijin Park, Jaeduk Han, Woorham Bae
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	clock generation duty cycle asynchronous sampling calibration analysis Electronics TK7800-8360
Acceso en línea:	https://doaj.org/article/00fc41f141dc4412a5e4a2a3aa82276b
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spelling	oai:doaj.org-article:00fc41f141dc4412a5e4a2a3aa82276b2021-11-11T15:37:29ZDesign and Analysis of Asynchronous Sampling Duty Cycle Corrector10.3390/electronics102125942079-9292https://doaj.org/article/00fc41f141dc4412a5e4a2a3aa82276b2021-10-01T00:00:00Zhttps://www.mdpi.com/2079-9292/10/21/2594https://doaj.org/toc/2079-9292This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling behavior of an asynchronous sampling duty cycle corrector is limited in some operation conditions, which degrades its robustness and performance. This paper, therefore, performs analysis on the settling behavior of the asynchronous sampling in various operating conditions and proposes a control scheme to avoid the lagged settling. To verify the proposed duty cycle corrector and its analysis, a prototype design is implemented in a 40-nm CMOS process and its performance is verified by post-layout simulations. The proposed duty cycle corrector achieved very small duty cycle errors (less than 0.8%) and consumed 540 uW per one DCC unit.Gijin ParkJaeduk HanWoorham BaeMDPI AGarticleclock generationduty cycleasynchronous samplingcalibrationanalysisElectronicsTK7800-8360ENElectronics, Vol 10, Iss 2594, p 2594 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	clock generation duty cycle asynchronous sampling calibration analysis Electronics TK7800-8360
spellingShingle	clock generation duty cycle asynchronous sampling calibration analysis Electronics TK7800-8360 Gijin Park Jaeduk Han Woorham Bae Design and Analysis of Asynchronous Sampling Duty Cycle Corrector
description	This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling behavior of an asynchronous sampling duty cycle corrector is limited in some operation conditions, which degrades its robustness and performance. This paper, therefore, performs analysis on the settling behavior of the asynchronous sampling in various operating conditions and proposes a control scheme to avoid the lagged settling. To verify the proposed duty cycle corrector and its analysis, a prototype design is implemented in a 40-nm CMOS process and its performance is verified by post-layout simulations. The proposed duty cycle corrector achieved very small duty cycle errors (less than 0.8%) and consumed 540 uW per one DCC unit.
format	article
author	Gijin Park Jaeduk Han Woorham Bae
author_facet	Gijin Park Jaeduk Han Woorham Bae
author_sort	Gijin Park
title	Design and Analysis of Asynchronous Sampling Duty Cycle Corrector
title_short	Design and Analysis of Asynchronous Sampling Duty Cycle Corrector
title_full	Design and Analysis of Asynchronous Sampling Duty Cycle Corrector
title_fullStr	Design and Analysis of Asynchronous Sampling Duty Cycle Corrector
title_full_unstemmed	Design and Analysis of Asynchronous Sampling Duty Cycle Corrector
title_sort	design and analysis of asynchronous sampling duty cycle corrector
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/00fc41f141dc4412a5e4a2a3aa82276b
work_keys_str_mv	AT gijinpark designandanalysisofasynchronoussamplingdutycyclecorrector AT jaedukhan designandanalysisofasynchronoussamplingdutycyclecorrector AT woorhambae designandanalysisofasynchronoussamplingdutycyclecorrector
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Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

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