An Optimum Structure of Scalable Capacitors in 3D Crosspoint Memory Technology
Memory chips need large capacitors in their periphery to drive boosted word-lines and bit-lines for read and write operations. In a previous work, scalable capacitors were proposed for 3D crosspoint memory to keep the area for the capacitors constant over technology generations. This paper proposes...
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| Autores principales: | , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
MDPI AG
2021
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/02703bbdf90f439dbcc60f6f02f5ba32 |
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| Sumario: | Memory chips need large capacitors in their periphery to drive boosted word-lines and bit-lines for read and write operations. In a previous work, scalable capacitors were proposed for 3D crosspoint memory to keep the area for the capacitors constant over technology generations. This paper proposes the capacitance models of three types of wiring capacitors: (1) vertical capacitor, (2) vertical and horizontal capacitor with next-neighbor wires connected with the other terminal, and (3) vertical and horizontal capacitor with next-neighbor pairs connected with the other terminal. These models are based on Wong’s crossover capacitor model to determine the capacitor structure with the highest capacitance density in 3D crosspoint memory technology. One can determine the best structure through optimizing the process parameters such as the height <i>H</i> of the insulation material between the metal wires and the thickness <i>T</i> of the metal wires and the design rules such as the width <i>W</i> and space <i>S</i> of metal wires. The model accuracy was in good agreement with the measurement of twelve types of capacitor structures fabricated in a 180 nm 6 metal standard CMOS process with the maximum error of 20%. Contour plots of the capacitance density across <i>H</i> vs. <i>S</i> where it is assumed that <i>W</i> = <i>T</i> = <i>S</i> are shown. As a result, the boundary condition regarding <i>H</i> and <i>S</i> is determined per 3D crosspoint memory technology with three, four, or five levels of wires. |
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