Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

Abstract Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electr...

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Autor principal:	Aryan Afzalian
Formato:	article
Lenguaje:	EN
Publicado:	Nature Portfolio 2021
Materias:	Materials of engineering and construction. Mechanics of materials TA401-492 Chemistry QD1-999
Acceso en línea:	https://doaj.org/article/02c9797c024848289326129a8cac622e
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spelling	oai:doaj.org-article:02c9797c024848289326129a8cac622e2021-12-02T18:11:52ZAb initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors10.1038/s41699-020-00181-12397-7132https://doaj.org/article/02c9797c024848289326129a8cac622e2021-01-01T00:00:00Zhttps://doi.org/10.1038/s41699-020-00181-1https://doaj.org/toc/2397-7132Abstract Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.Aryan AfzalianNature PortfolioarticleMaterials of engineering and construction. Mechanics of materialsTA401-492ChemistryQD1-999ENnpj 2D Materials and Applications, Vol 5, Iss 1, Pp 1-13 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Materials of engineering and construction. Mechanics of materials TA401-492 Chemistry QD1-999
spellingShingle	Materials of engineering and construction. Mechanics of materials TA401-492 Chemistry QD1-999 Aryan Afzalian Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors
description	Abstract Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.
format	article
author	Aryan Afzalian
author_facet	Aryan Afzalian
author_sort	Aryan Afzalian
title	Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors
title_short	Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors
title_full	Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors
title_fullStr	Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors
title_full_unstemmed	Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors
title_sort	ab initio perspective of ultra-scaled cmos from 2d-material fundamentals to dynamically doped transistors
publisher	Nature Portfolio
publishDate	2021
url	https://doaj.org/article/02c9797c024848289326129a8cac622e
work_keys_str_mv	AT aryanafzalian abinitioperspectiveofultrascaledcmosfrom2dmaterialfundamentalstodynamicallydopedtransistors
_version_	1718378551291412480

Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

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