Design and Implementation of High Frequency and Low-Power Phase-locked Loop

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency d...

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Autores principales:	Premananda B. S., Dhanush T. N., Vaishnavi S. Parashar, D. Aneesh Bharadwaj
Formato:	article
Lenguaje:	EN
Publicado:	Universidade do Porto 2021
Materias:	charge pump cmos csvco pfd pll vco Engineering (General). Civil engineering (General) TA1-2040 Technology (General) T1-995
Acceso en línea:	https://doaj.org/article/0398a13a4bf94cf58812ac692f8ac491
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spelling	oai:doaj.org-article:0398a13a4bf94cf58812ac692f8ac4912021-11-26T12:34:56ZDesign and Implementation of High Frequency and Low-Power Phase-locked Loop2183-649310.24840/2183-6493_007.004_0006https://doaj.org/article/0398a13a4bf94cf58812ac692f8ac4912021-11-01T00:00:00Zhttps://journalengineering.fe.up.pt/index.php/upjeng/article/view/928https://doaj.org/toc/2183-6493Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.Premananda B. S.Dhanush T. N.Vaishnavi S. ParasharD. Aneesh BharadwajUniversidade do Portoarticlecharge pumpcmoscsvcopfdpllvcoEngineering (General). Civil engineering (General)TA1-2040Technology (General)T1-995ENU.Porto Journal of Engineering, Vol 7, Iss 4, Pp 70-86 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	charge pump cmos csvco pfd pll vco Engineering (General). Civil engineering (General) TA1-2040 Technology (General) T1-995
spellingShingle	charge pump cmos csvco pfd pll vco Engineering (General). Civil engineering (General) TA1-2040 Technology (General) T1-995 Premananda B. S. Dhanush T. N. Vaishnavi S. Parashar D. Aneesh Bharadwaj Design and Implementation of High Frequency and Low-Power Phase-locked Loop
description	Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.
format	article
author	Premananda B. S. Dhanush T. N. Vaishnavi S. Parashar D. Aneesh Bharadwaj
author_facet	Premananda B. S. Dhanush T. N. Vaishnavi S. Parashar D. Aneesh Bharadwaj
author_sort	Premananda B. S.
title	Design and Implementation of High Frequency and Low-Power Phase-locked Loop
title_short	Design and Implementation of High Frequency and Low-Power Phase-locked Loop
title_full	Design and Implementation of High Frequency and Low-Power Phase-locked Loop
title_fullStr	Design and Implementation of High Frequency and Low-Power Phase-locked Loop
title_full_unstemmed	Design and Implementation of High Frequency and Low-Power Phase-locked Loop
title_sort	design and implementation of high frequency and low-power phase-locked loop
publisher	Universidade do Porto
publishDate	2021
url	https://doaj.org/article/0398a13a4bf94cf58812ac692f8ac491
work_keys_str_mv	AT premanandabs designandimplementationofhighfrequencyandlowpowerphaselockedloop AT dhanushtn designandimplementationofhighfrequencyandlowpowerphaselockedloop AT vaishnavisparashar designandimplementationofhighfrequencyandlowpowerphaselockedloop AT daneeshbharadwaj designandimplementationofhighfrequencyandlowpowerphaselockedloop
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Design and Implementation of High Frequency and Low-Power Phase-locked Loop

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