Design and Implementation of High Frequency and Low-Power Phase-locked Loop
Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency d...
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| Autores principales: | , , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
Universidade do Porto
2021
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/0398a13a4bf94cf58812ac692f8ac491 |
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