An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a...

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Autores principales:	B. Srinath, Rajesh Verma, Abdulwasa Bakr Barnawi, Ramkumar Raja, Mohammed Abdul Muqeet, Neeraj Kumar Shukla, A. Ananthi Christy, C. Bharatiraja, Josiah Lange Munda
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	timing constraint multiple supply voltage physical design floorplanning Electronics TK7800-8360
Acceso en línea:	https://doaj.org/article/053e0288fa2449afa95d959cdf374d84
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spelling	oai:doaj.org-article:053e0288fa2449afa95d959cdf374d842021-11-25T17:24:43ZAn Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts10.3390/electronics102227952079-9292https://doaj.org/article/053e0288fa2449afa95d959cdf374d842021-11-01T00:00:00Zhttps://www.mdpi.com/2079-9292/10/22/2795https://doaj.org/toc/2079-9292Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.B. SrinathRajesh VermaAbdulwasa Bakr BarnawiRamkumar RajaMohammed Abdul MuqeetNeeraj Kumar ShuklaA. Ananthi ChristyC. BharatirajaJosiah Lange MundaMDPI AGarticletiming constraintmultiple supply voltagephysical designfloorplanningElectronicsTK7800-8360ENElectronics, Vol 10, Iss 2795, p 2795 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	timing constraint multiple supply voltage physical design floorplanning Electronics TK7800-8360
spellingShingle	timing constraint multiple supply voltage physical design floorplanning Electronics TK7800-8360 B. Srinath Rajesh Verma Abdulwasa Bakr Barnawi Ramkumar Raja Mohammed Abdul Muqeet Neeraj Kumar Shukla A. Ananthi Christy C. Bharatiraja Josiah Lange Munda An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts
description	Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.
format	article
author	B. Srinath Rajesh Verma Abdulwasa Bakr Barnawi Ramkumar Raja Mohammed Abdul Muqeet Neeraj Kumar Shukla A. Ananthi Christy C. Bharatiraja Josiah Lange Munda
author_facet	B. Srinath Rajesh Verma Abdulwasa Bakr Barnawi Ramkumar Raja Mohammed Abdul Muqeet Neeraj Kumar Shukla A. Ananthi Christy C. Bharatiraja Josiah Lange Munda
author_sort	B. Srinath
title	An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts
title_short	An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts
title_full	An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts
title_fullStr	An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts
title_full_unstemmed	An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts
title_sort	investigation of clock skew using a wirelength-aware floorplanning process in the pre-placement stages of msv layouts
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/053e0288fa2449afa95d959cdf374d84
work_keys_str_mv	AT bsrinath aninvestigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT rajeshverma aninvestigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT abdulwasabakrbarnawi aninvestigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT ramkumarraja aninvestigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT mohammedabdulmuqeet aninvestigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT neerajkumarshukla aninvestigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT aananthichristy aninvestigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT cbharatiraja aninvestigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT josiahlangemunda aninvestigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT bsrinath investigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT rajeshverma investigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT abdulwasabakrbarnawi investigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT ramkumarraja investigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT mohammedabdulmuqeet investigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT neerajkumarshukla investigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT aananthichristy investigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT cbharatiraja investigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts AT josiahlangemunda investigationofclockskewusingawirelengthawarefloorplanningprocessinthepreplacementstagesofmsvlayouts
_version_	1718412388151066624

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

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