An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a...

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Autores principales: B. Srinath, Rajesh Verma, Abdulwasa Bakr Barnawi, Ramkumar Raja, Mohammed Abdul Muqeet, Neeraj Kumar Shukla, A. Ananthi Christy, C. Bharatiraja, Josiah Lange Munda
Formato: article
Lenguaje:EN
Publicado: MDPI AG 2021
Materias:
timing constraint
multiple supply voltage
physical design
floorplanning
Electronics
TK7800-8360
Acceso en línea:https://doaj.org/article/053e0288fa2449afa95d959cdf374d84
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https://doaj.org/article/053e0288fa2449afa95d959cdf374d84

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