A Performance Evaluation of DRAM Access for In-Memory Databases

The latest CPUs(computer cpu processors) employ multiple cores, massively superscalar pipelines, out-of-order execution of tons of instructions, and advanced SIMD capabilities, which can hide the memory access latency. And most of recent memory-oriented data structures have already benefit from thes...

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Autores principales:	Zhang Qian, Jianhao Wei, Yiwen Xiang, Chuqiao Xiao
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	DRAM access in-memory databases data structure MMDBs database techniques Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/10eaab3c3f9e4f478106368b64ab673f
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id	oai:doaj.org-article:10eaab3c3f9e4f478106368b64ab673f
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spelling	oai:doaj.org-article:10eaab3c3f9e4f478106368b64ab673f2021-11-09T00:03:13ZA Performance Evaluation of DRAM Access for In-Memory Databases2169-353610.1109/ACCESS.2021.3123379https://doaj.org/article/10eaab3c3f9e4f478106368b64ab673f2021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9590497/https://doaj.org/toc/2169-3536The latest CPUs(computer cpu processors) employ multiple cores, massively superscalar pipelines, out-of-order execution of tons of instructions, and advanced SIMD capabilities, which can hide the memory access latency. And most of recent memory-oriented data structures have already benefit from these features. However, due to the complexity of data organization, these CPUs do not always work well in memory resident database systems (MMDBs), particularly regarding storing data in dynamic random-access memory (DRAM). This article studies memory-efficient data structures by analyzing the run time, access latency, cache misses, instructions per cycle (IPC), and DRAM reads (bytes). Then, we design and implement two data organization schemas in the main memory database: dispersing data block organization and clustering data block organization. Using algorithmic engineering and careful attention to internal parallelism, cache alignment can hide the memory access latency. However, we find that these data structures work well in some cases, though they have been eclipsed in the face of complex access paths. To determine the reasons, we study the impact of database techniques on memory access latency, such as data partitioning, storage models, and by processing algorithms. With the specific main memory database system, we estimate the performance of each data organization schema based on DRAM DDR4 and the latest Intel Haswell microarchitecture. In conclusion, this work will make DRAM access applicable in real-world situations by implementing the schema to systems, such as in-memory databases.Zhang QianJianhao WeiYiwen XiangChuqiao XiaoIEEEarticleDRAM accessin-memory databasesdata structureMMDBsdatabase techniquesElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Access, Vol 9, Pp 146454-146470 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	DRAM access in-memory databases data structure MMDBs database techniques Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	DRAM access in-memory databases data structure MMDBs database techniques Electrical engineering. Electronics. Nuclear engineering TK1-9971 Zhang Qian Jianhao Wei Yiwen Xiang Chuqiao Xiao A Performance Evaluation of DRAM Access for In-Memory Databases
description	The latest CPUs(computer cpu processors) employ multiple cores, massively superscalar pipelines, out-of-order execution of tons of instructions, and advanced SIMD capabilities, which can hide the memory access latency. And most of recent memory-oriented data structures have already benefit from these features. However, due to the complexity of data organization, these CPUs do not always work well in memory resident database systems (MMDBs), particularly regarding storing data in dynamic random-access memory (DRAM). This article studies memory-efficient data structures by analyzing the run time, access latency, cache misses, instructions per cycle (IPC), and DRAM reads (bytes). Then, we design and implement two data organization schemas in the main memory database: dispersing data block organization and clustering data block organization. Using algorithmic engineering and careful attention to internal parallelism, cache alignment can hide the memory access latency. However, we find that these data structures work well in some cases, though they have been eclipsed in the face of complex access paths. To determine the reasons, we study the impact of database techniques on memory access latency, such as data partitioning, storage models, and by processing algorithms. With the specific main memory database system, we estimate the performance of each data organization schema based on DRAM DDR4 and the latest Intel Haswell microarchitecture. In conclusion, this work will make DRAM access applicable in real-world situations by implementing the schema to systems, such as in-memory databases.
format	article
author	Zhang Qian Jianhao Wei Yiwen Xiang Chuqiao Xiao
author_facet	Zhang Qian Jianhao Wei Yiwen Xiang Chuqiao Xiao
author_sort	Zhang Qian
title	A Performance Evaluation of DRAM Access for In-Memory Databases
title_short	A Performance Evaluation of DRAM Access for In-Memory Databases
title_full	A Performance Evaluation of DRAM Access for In-Memory Databases
title_fullStr	A Performance Evaluation of DRAM Access for In-Memory Databases
title_full_unstemmed	A Performance Evaluation of DRAM Access for In-Memory Databases
title_sort	performance evaluation of dram access for in-memory databases
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/10eaab3c3f9e4f478106368b64ab673f
work_keys_str_mv	AT zhangqian aperformanceevaluationofdramaccessforinmemorydatabases AT jianhaowei aperformanceevaluationofdramaccessforinmemorydatabases AT yiwenxiang aperformanceevaluationofdramaccessforinmemorydatabases AT chuqiaoxiao aperformanceevaluationofdramaccessforinmemorydatabases AT zhangqian performanceevaluationofdramaccessforinmemorydatabases AT jianhaowei performanceevaluationofdramaccessforinmemorydatabases AT yiwenxiang performanceevaluationofdramaccessforinmemorydatabases AT chuqiaoxiao performanceevaluationofdramaccessforinmemorydatabases
_version_	1718441361097621504

A Performance Evaluation of DRAM Access for In-Memory Databases

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