A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM
This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to av...
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| Autores principales: | , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
MDPI AG
2021
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f40 |
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| Sumario: | This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>251.6</mn></mrow></semantics></math></inline-formula> dB FoM. |
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