A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM
This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to av...
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2021
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oai:doaj.org-article:1362c36475e14fa1bfb6e948908c7f402021-11-25T18:58:12ZA 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM10.3390/s212276481424-8220https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f402021-11-01T00:00:00Zhttps://www.mdpi.com/1424-8220/21/22/7648https://doaj.org/toc/1424-8220This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>251.6</mn></mrow></semantics></math></inline-formula> dB FoM.Shi ZuoJianzhong ZhaoYumei ZhouMDPI AGarticleSSPLLhybrid dual path looplow jitterlow power consumptionChemical technologyTP1-1185ENSensors, Vol 21, Iss 7648, p 7648 (2021) |
| institution |
DOAJ |
| collection |
DOAJ |
| language |
EN |
| topic |
SSPLL hybrid dual path loop low jitter low power consumption Chemical technology TP1-1185 |
| spellingShingle |
SSPLL hybrid dual path loop low jitter low power consumption Chemical technology TP1-1185 Shi Zuo Jianzhong Zhao Yumei Zhou A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| description |
This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>251.6</mn></mrow></semantics></math></inline-formula> dB FoM. |
| format |
article |
| author |
Shi Zuo Jianzhong Zhao Yumei Zhou |
| author_facet |
Shi Zuo Jianzhong Zhao Yumei Zhou |
| author_sort |
Shi Zuo |
| title |
A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_short |
A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_full |
A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_fullStr |
A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_full_unstemmed |
A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_sort |
0.8 v, 5.3–5.9 ghz sub-sampling pll with 196.5 fs<sub><i>rms</i></sub> integrated jitter and −251.6 db fom |
| publisher |
MDPI AG |
| publishDate |
2021 |
| url |
https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f40 |
| work_keys_str_mv |
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