A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM

A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM

This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to av...

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Detalles Bibliográficos
Autores principales: Shi Zuo, Jianzhong Zhao, Yumei Zhou
Formato: article
Lenguaje:EN
Publicado: MDPI AG 2021
Materias:
SSPLL
hybrid dual path loop
low jitter
low power consumption
Chemical technology
TP1-1185
Acceso en línea:https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f40
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