Temporal Accelerators: Unleashing the Potential of Embedded FPGAs
When the complexity of a problem rises, its solution requires more hardware resources. A usual way to solve this is to use larger processors and add more memory. When using Field Programmable Gate-Arrays (FPGAs), which can instantiate arbitrary circuit designs, a larger, mo...
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Graz University of Technology
2021
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oai:doaj.org-article:24ff81af55b0430dbcd8f0816bee418a2021-11-30T04:30:10ZTemporal Accelerators: Unleashing the Potential of Embedded FPGAs10.3897/jucs.772470948-6968https://doaj.org/article/24ff81af55b0430dbcd8f0816bee418a2021-11-01T00:00:00Zhttps://lib.jucs.org/article/77247/download/pdf/https://lib.jucs.org/article/77247/download/xml/https://lib.jucs.org/article/77247/https://doaj.org/toc/0948-6968When the complexity of a problem rises, its solution requires more hardware resources. A usual way to solve this is to use larger processors and add more memory. When using Field Programmable Gate-Arrays (FPGAs), which can instantiate arbitrary circuit designs, a larger, more costly and power hungry chip is used. In this paper we propose a different approach, namely to split the problem into a graph of interdependent smaller tasks and to reconfigure a small FPGA during runtime to execute each of these tasks efficiently sequentially. This can result in cheaper and more energy efficient systems that can execute very complex problems locally. We present a basic analytical model, evaluate its accuracy and discuss initial insight from it.Christopher CichiwskyjGregor SchieleGraz University of TechnologyarticleIoTEmbeddedFPGAReconfigurable HardwareElectronic computers. Computer scienceQA75.5-76.95ENJournal of Universal Computer Science, Vol 27, Iss 11, Pp 1174-1192 (2021) |
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IoT Embedded FPGA Reconfigurable Hardware Electronic computers. Computer science QA75.5-76.95 |
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IoT Embedded FPGA Reconfigurable Hardware Electronic computers. Computer science QA75.5-76.95 Christopher Cichiwskyj Gregor Schiele Temporal Accelerators: Unleashing the Potential of Embedded FPGAs |
description |
When the complexity of a problem rises, its solution requires more hardware resources. A usual way to solve this is to use larger processors and add more memory. When using Field Programmable Gate-Arrays (FPGAs), which can instantiate arbitrary circuit designs, a larger, more costly and power hungry chip is used. In this paper we propose a different approach, namely to split the problem into a graph of interdependent smaller tasks and to reconfigure a small FPGA during runtime to execute each of these tasks efficiently sequentially. This can result in cheaper and more energy efficient systems that can execute very complex problems locally. We present a basic analytical model, evaluate its accuracy and discuss initial insight from it. |
format |
article |
author |
Christopher Cichiwskyj Gregor Schiele |
author_facet |
Christopher Cichiwskyj Gregor Schiele |
author_sort |
Christopher Cichiwskyj |
title |
Temporal Accelerators: Unleashing the Potential of Embedded FPGAs |
title_short |
Temporal Accelerators: Unleashing the Potential of Embedded FPGAs |
title_full |
Temporal Accelerators: Unleashing the Potential of Embedded FPGAs |
title_fullStr |
Temporal Accelerators: Unleashing the Potential of Embedded FPGAs |
title_full_unstemmed |
Temporal Accelerators: Unleashing the Potential of Embedded FPGAs |
title_sort |
temporal accelerators: unleashing the potential of embedded fpgas |
publisher |
Graz University of Technology |
publishDate |
2021 |
url |
https://doaj.org/article/24ff81af55b0430dbcd8f0816bee418a |
work_keys_str_mv |
AT christophercichiwskyj temporalacceleratorsunleashingthepotentialofembeddedfpgas AT gregorschiele temporalacceleratorsunleashingthepotentialofembeddedfpgas |
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1718406733013975040 |