Design of a BIST implemented AES crypto-processor ASIC.

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing...

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Autores principales:	Md Liakot Ali, Md Shazzatur Rahman, Fakir Sharif Hossain
Formato:	article
Lenguaje:	EN
Publicado:	Public Library of Science (PLoS) 2021
Materias:	Medicine R Science Q
Acceso en línea:	https://doaj.org/article/29a3abaf94e446f3b4281dad1f69d446
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spelling	oai:doaj.org-article:29a3abaf94e446f3b4281dad1f69d4462021-12-02T20:12:59ZDesign of a BIST implemented AES crypto-processor ASIC.1932-620310.1371/journal.pone.0259956https://doaj.org/article/29a3abaf94e446f3b4281dad1f69d4462021-01-01T00:00:00Zhttps://doi.org/10.1371/journal.pone.0259956https://doaj.org/toc/1932-6203This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.Md Liakot AliMd Shazzatur RahmanFakir Sharif HossainPublic Library of Science (PLoS)articleMedicineRScienceQENPLoS ONE, Vol 16, Iss 11, p e0259956 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Medicine R Science Q
spellingShingle	Medicine R Science Q Md Liakot Ali Md Shazzatur Rahman Fakir Sharif Hossain Design of a BIST implemented AES crypto-processor ASIC.
description	This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.
format	article
author	Md Liakot Ali Md Shazzatur Rahman Fakir Sharif Hossain
author_facet	Md Liakot Ali Md Shazzatur Rahman Fakir Sharif Hossain
author_sort	Md Liakot Ali
title	Design of a BIST implemented AES crypto-processor ASIC.
title_short	Design of a BIST implemented AES crypto-processor ASIC.
title_full	Design of a BIST implemented AES crypto-processor ASIC.
title_fullStr	Design of a BIST implemented AES crypto-processor ASIC.
title_full_unstemmed	Design of a BIST implemented AES crypto-processor ASIC.
title_sort	design of a bist implemented aes crypto-processor asic.
publisher	Public Library of Science (PLoS)
publishDate	2021
url	https://doaj.org/article/29a3abaf94e446f3b4281dad1f69d446
work_keys_str_mv	AT mdliakotali designofabistimplementedaescryptoprocessorasic AT mdshazzaturrahman designofabistimplementedaescryptoprocessorasic AT fakirsharifhossain designofabistimplementedaescryptoprocessorasic
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Design of a BIST implemented AES crypto-processor ASIC.

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