Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure

Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these systems, cryptographic accelerators are integrated with processor cores to provide users with the software’s flexibility and hardware’s high performance. First, this work aimed to confirm the vuln...

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Autores principales: Ba-Anh Dao, Trong-Thuc Hoang, Anh-Tien Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
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Publicado: IEEE 2021
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Acceso en línea:https://doaj.org/article/36ee190b07044c1ba9e2c48d443dc18d
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spelling oai:doaj.org-article:36ee190b07044c1ba9e2c48d443dc18d2021-11-18T00:00:54ZCorrelation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure2169-353610.1109/ACCESS.2021.3126703https://doaj.org/article/36ee190b07044c1ba9e2c48d443dc18d2021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9610048/https://doaj.org/toc/2169-3536Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these systems, cryptographic accelerators are integrated with processor cores to provide users with the software’s flexibility and hardware’s high performance. First, this work aimed to confirm the vulnerability of cryptographic SoCs against several types of power analysis attacks. Then, the novel Random Dynamic Frequency Scaling (RDFS) countermeasure is proposed to improve the resistance of such systems. The proposed RDFS countermeasure improved the power analysis resistance while maintaining low-performance overhead and hardware costs by generating more than 219,000 distinct frequencies for driving only the cryptographic accelerators. The effectiveness of the proposed RDFS countermeasure is demonstrated by conducting realistic Correlation Power Analysis (CPA) attacks, Deep-Learning-based Side-Channel Analysis (DL-SCA) attacks, and Test Vector Leakage Assessment (TVLA) testing methodology. The experimental results show that the RISC-V SoC protected by RDFS countermeasure can withstand CPA attacks and TVLA test with more than five million power traces, which is the best result compared to other related works. The proposed RDFS countermeasure also harden the targeted RISC-V SoC’s resistance against DL-SCA attacks.Ba-Anh DaoTrong-Thuc HoangAnh-Tien LeAkira TsukamotoKuniyasu SuzakiCong-Kha PhamIEEEarticleSide-channel attackscorrelation power analysis attacksdeep learning based side-channel attackscountermeasureRISC-VElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Access, Vol 9, Pp 151993-152014 (2021)
institution DOAJ
collection DOAJ
language EN
topic Side-channel attacks
correlation power analysis attacks
deep learning based side-channel attacks
countermeasure
RISC-V
Electrical engineering. Electronics. Nuclear engineering
TK1-9971
spellingShingle Side-channel attacks
correlation power analysis attacks
deep learning based side-channel attacks
countermeasure
RISC-V
Electrical engineering. Electronics. Nuclear engineering
TK1-9971
Ba-Anh Dao
Trong-Thuc Hoang
Anh-Tien Le
Akira Tsukamoto
Kuniyasu Suzaki
Cong-Kha Pham
Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure
description Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these systems, cryptographic accelerators are integrated with processor cores to provide users with the software’s flexibility and hardware’s high performance. First, this work aimed to confirm the vulnerability of cryptographic SoCs against several types of power analysis attacks. Then, the novel Random Dynamic Frequency Scaling (RDFS) countermeasure is proposed to improve the resistance of such systems. The proposed RDFS countermeasure improved the power analysis resistance while maintaining low-performance overhead and hardware costs by generating more than 219,000 distinct frequencies for driving only the cryptographic accelerators. The effectiveness of the proposed RDFS countermeasure is demonstrated by conducting realistic Correlation Power Analysis (CPA) attacks, Deep-Learning-based Side-Channel Analysis (DL-SCA) attacks, and Test Vector Leakage Assessment (TVLA) testing methodology. The experimental results show that the RISC-V SoC protected by RDFS countermeasure can withstand CPA attacks and TVLA test with more than five million power traces, which is the best result compared to other related works. The proposed RDFS countermeasure also harden the targeted RISC-V SoC’s resistance against DL-SCA attacks.
format article
author Ba-Anh Dao
Trong-Thuc Hoang
Anh-Tien Le
Akira Tsukamoto
Kuniyasu Suzaki
Cong-Kha Pham
author_facet Ba-Anh Dao
Trong-Thuc Hoang
Anh-Tien Le
Akira Tsukamoto
Kuniyasu Suzaki
Cong-Kha Pham
author_sort Ba-Anh Dao
title Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure
title_short Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure
title_full Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure
title_fullStr Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure
title_full_unstemmed Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure
title_sort correlation power analysis attack resisted cryptographic risc-v soc with random dynamic frequency scaling countermeasure
publisher IEEE
publishDate 2021
url https://doaj.org/article/36ee190b07044c1ba9e2c48d443dc18d
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