Scalable Arrays of Micro-Penning Traps for Quantum Computing and Simulation

We propose the use of two-dimensional Penning trap arrays as a scalable platform for quantum simulation and quantum computing with trapped atomic ions. This approach involves placing arrays of microstructured electrodes defining static electric quadrupole sites in a magnetic field, with single ions...

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Autores principales: S. Jain, J. Alonso, M. Grau, J. P. Home
Formato: article
Lenguaje:EN
Publicado: American Physical Society 2020
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Acceso en línea:https://doaj.org/article/3fe559a0b34f4b9eb3518e42c77ae95c
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Sumario:We propose the use of two-dimensional Penning trap arrays as a scalable platform for quantum simulation and quantum computing with trapped atomic ions. This approach involves placing arrays of microstructured electrodes defining static electric quadrupole sites in a magnetic field, with single ions trapped at each site and coupled to neighbors via the Coulomb interaction. We solve for the normal modes of ion motion in such arrays and derive a generalized multi-ion invariance theorem for stable motion even in the presence of trap imperfections. We use these techniques to investigate the feasibility of quantum simulation and quantum computation in fixed ion lattices. In homogeneous arrays, we show that sufficiently dense arrays are achievable, with axial, magnetron, and cyclotron motions exhibiting interion dipolar coupling with rates significantly higher than expected decoherence. With the addition of laser fields, these can realize tunable-range interacting spin Hamiltonians. We also show how local control of potentials allows isolation of small numbers of ions in a fixed array and can be used to implement high-fidelity gates. The use of static trapping fields means that our approach is not limited by power requirements as the system size increases, removing a major challenge for scaling which is present in standard radio-frequency traps. Thus, the architecture and methods provided here appear to open a path for trapped-ion quantum computing to reach fault-tolerant scale devices.