Hardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology

The increment in the use of high-resolution imaging sensors on-board satellites motivates the use of on-board image compression, mainly due to restrictions in terms of both hardware (computational and storage resources) and downlink bandwidth with the ground. This work presents a compression solutio...

Descripción completa

Guardado en:

Detalles Bibliográficos
Autores principales:	Yubal Barrios, Antonio Sánchez, Raúl Guerra, Roberto Sarmiento
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	hyperspectral imaging compression algorithms FPGA hardware implementations space missions on-board data processing Science Q
Acceso en línea:	https://doaj.org/article/42cd5d0184c74114b133e81cb457cc78
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

id	oai:doaj.org-article:42cd5d0184c74114b133e81cb457cc78
record_format	dspace
spelling	oai:doaj.org-article:42cd5d0184c74114b133e81cb457cc782021-11-11T18:55:12ZHardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology10.3390/rs132143882072-4292https://doaj.org/article/42cd5d0184c74114b133e81cb457cc782021-10-01T00:00:00Zhttps://www.mdpi.com/2072-4292/13/21/4388https://doaj.org/toc/2072-4292The increment in the use of high-resolution imaging sensors on-board satellites motivates the use of on-board image compression, mainly due to restrictions in terms of both hardware (computational and storage resources) and downlink bandwidth with the ground. This work presents a compression solution based on the CCSDS 123.0-B-2 near-lossless compression standard for multi- and hyperspectral images, which deals with the high amount of data acquired by these next-generation sensors. The proposed approach has been developed following an HLS design methodology, accelerating design time and obtaining good system performance. The compressor is comprised by two main stages, a predictor and a hybrid encoder, designed in Band-Interleaved by Line (BIL) order and optimized to achieve a trade-off between throughput and logic resources utilization. This solution has been mapped on a Xilinx Kintex UltraScale XCKU040 FPGA and targeting AVIRIS images, reaching a throughput of 12.5 MSamples/s and consuming only the 7% of LUTs and around the 14% of dedicated memory blocks available in the device. To the best of our knowledge, this is the first fully-compliant hardware implementation of the CCSDS 123.0-B-2 near-lossless compression standard available in the state of the art.Yubal BarriosAntonio SánchezRaúl GuerraRoberto SarmientoMDPI AGarticlehyperspectral imagingcompression algorithmsFPGAhardware implementationsspace missionson-board data processingScienceQENRemote Sensing, Vol 13, Iss 4388, p 4388 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	hyperspectral imaging compression algorithms FPGA hardware implementations space missions on-board data processing Science Q
spellingShingle	hyperspectral imaging compression algorithms FPGA hardware implementations space missions on-board data processing Science Q Yubal Barrios Antonio Sánchez Raúl Guerra Roberto Sarmiento Hardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology
description	The increment in the use of high-resolution imaging sensors on-board satellites motivates the use of on-board image compression, mainly due to restrictions in terms of both hardware (computational and storage resources) and downlink bandwidth with the ground. This work presents a compression solution based on the CCSDS 123.0-B-2 near-lossless compression standard for multi- and hyperspectral images, which deals with the high amount of data acquired by these next-generation sensors. The proposed approach has been developed following an HLS design methodology, accelerating design time and obtaining good system performance. The compressor is comprised by two main stages, a predictor and a hybrid encoder, designed in Band-Interleaved by Line (BIL) order and optimized to achieve a trade-off between throughput and logic resources utilization. This solution has been mapped on a Xilinx Kintex UltraScale XCKU040 FPGA and targeting AVIRIS images, reaching a throughput of 12.5 MSamples/s and consuming only the 7% of LUTs and around the 14% of dedicated memory blocks available in the device. To the best of our knowledge, this is the first fully-compliant hardware implementation of the CCSDS 123.0-B-2 near-lossless compression standard available in the state of the art.
format	article
author	Yubal Barrios Antonio Sánchez Raúl Guerra Roberto Sarmiento
author_facet	Yubal Barrios Antonio Sánchez Raúl Guerra Roberto Sarmiento
author_sort	Yubal Barrios
title	Hardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology
title_short	Hardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology
title_full	Hardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology
title_fullStr	Hardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology
title_full_unstemmed	Hardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology
title_sort	hardware implementation of the ccsds 123.0-b-2 near-lossless compression standard following an hls design methodology
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/42cd5d0184c74114b133e81cb457cc78
work_keys_str_mv	AT yubalbarrios hardwareimplementationoftheccsds1230b2nearlosslesscompressionstandardfollowinganhlsdesignmethodology AT antoniosanchez hardwareimplementationoftheccsds1230b2nearlosslesscompressionstandardfollowinganhlsdesignmethodology AT raulguerra hardwareimplementationoftheccsds1230b2nearlosslesscompressionstandardfollowinganhlsdesignmethodology AT robertosarmiento hardwareimplementationoftheccsds1230b2nearlosslesscompressionstandardfollowinganhlsdesignmethodology
_version_	1718431640012718080

Hardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology

Ejemplares similares