Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

Convolutional Neural Network (CNN) has attained high accuracy and it has been widely employed in image recognition tasks. In recent times, deep learning-based modern applications are evolving and it poses a challenge in research and development of hardware implementation. Therefore, hardware optimiz...

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Autores principales:	Fasih Ud Din Farrukh, Chun Zhang, Yancao Jiang, Zhonghan Zhang, Ziqiang Wang, Zhihua Wang, Hanjun Jiang
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2020
Materias:	Convolutional neural network booth encoding multiplier WALLACE tree adders FPGA adder tree object detection Electric apparatus and materials. Electric circuits. Electric networks TK452-454.4
Acceso en línea:	https://doaj.org/article/4399c3d1392f42e6857ae5b3ac56c332
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id	oai:doaj.org-article:4399c3d1392f42e6857ae5b3ac56c332
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spelling	oai:doaj.org-article:4399c3d1392f42e6857ae5b3ac56c3322021-11-20T00:03:12ZPower Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders2644-122510.1109/OJCAS.2020.3007334https://doaj.org/article/4399c3d1392f42e6857ae5b3ac56c3322020-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9134378/https://doaj.org/toc/2644-1225Convolutional Neural Network (CNN) has attained high accuracy and it has been widely employed in image recognition tasks. In recent times, deep learning-based modern applications are evolving and it poses a challenge in research and development of hardware implementation. Therefore, hardware optimization for efficient accelerator design of CNN remains a challenging task. A key component of the accelerator design is a processing element (PE) that implements the convolution operation. To reduce the amount of hardware resources and power consumption, this article provides a new processing element design as an alternate solution for hardware implementation. Modified BOOTH encoding (MBE) multiplier and WALLACE tree-based adders are proposed to replace bulky MAC units and typical adder tree respectively. The proposed CNN accelerator design is tested on Zynq-706 FPGA board which achieves a throughput of 87.03 GOP/s for Tiny-YOLO-v2 architecture. The proposed design allows to reduce hardware costs by 24.5% achieving a power efficiency of 61.64 GOP/s/W that outperforms the previous designs.Fasih Ud Din FarrukhChun ZhangYancao JiangZhonghan ZhangZiqiang WangZhihua WangHanjun JiangIEEEarticleConvolutional neural networkbooth encoding multiplierWALLACE tree addersFPGAadder treeobject detectionElectric apparatus and materials. Electric circuits. Electric networksTK452-454.4ENIEEE Open Journal of Circuits and Systems, Vol 1, Pp 76-87 (2020)
institution	DOAJ
collection	DOAJ
language	EN
topic	Convolutional neural network booth encoding multiplier WALLACE tree adders FPGA adder tree object detection Electric apparatus and materials. Electric circuits. Electric networks TK452-454.4
spellingShingle	Convolutional neural network booth encoding multiplier WALLACE tree adders FPGA adder tree object detection Electric apparatus and materials. Electric circuits. Electric networks TK452-454.4 Fasih Ud Din Farrukh Chun Zhang Yancao Jiang Zhonghan Zhang Ziqiang Wang Zhihua Wang Hanjun Jiang Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders
description	Convolutional Neural Network (CNN) has attained high accuracy and it has been widely employed in image recognition tasks. In recent times, deep learning-based modern applications are evolving and it poses a challenge in research and development of hardware implementation. Therefore, hardware optimization for efficient accelerator design of CNN remains a challenging task. A key component of the accelerator design is a processing element (PE) that implements the convolution operation. To reduce the amount of hardware resources and power consumption, this article provides a new processing element design as an alternate solution for hardware implementation. Modified BOOTH encoding (MBE) multiplier and WALLACE tree-based adders are proposed to replace bulky MAC units and typical adder tree respectively. The proposed CNN accelerator design is tested on Zynq-706 FPGA board which achieves a throughput of 87.03 GOP/s for Tiny-YOLO-v2 architecture. The proposed design allows to reduce hardware costs by 24.5% achieving a power efficiency of 61.64 GOP/s/W that outperforms the previous designs.
format	article
author	Fasih Ud Din Farrukh Chun Zhang Yancao Jiang Zhonghan Zhang Ziqiang Wang Zhihua Wang Hanjun Jiang
author_facet	Fasih Ud Din Farrukh Chun Zhang Yancao Jiang Zhonghan Zhang Ziqiang Wang Zhihua Wang Hanjun Jiang
author_sort	Fasih Ud Din Farrukh
title	Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders
title_short	Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders
title_full	Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders
title_fullStr	Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders
title_full_unstemmed	Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders
title_sort	power efficient tiny yolo cnn using reduced hardware resources based on booth multiplier and wallace tree adders
publisher	IEEE
publishDate	2020
url	https://doaj.org/article/4399c3d1392f42e6857ae5b3ac56c332
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Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

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