Reduction of the error in the hardware neural network

Specialized hardware implementations of Artificial Neural Networks (ANNs) can offer faster execution than general-purpose microprocessors by taking advantage of reusable modules, parallel processes and specialized computational components. Modern high-density Field Programmable Gate Arrays (FPGAs)...

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Autor principal:	Dhafer r. Zaghar
Formato:	article
Lenguaje:	EN
Publicado:	Al-Khwarizmi College of Engineering – University of Baghdad 2007
Materias:	Chemical engineering TP155-156 Engineering (General). Civil engineering (General) TA1-2040
Acceso en línea:	https://doaj.org/article/44d3932206954187abef1a352f117c5d
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spelling	oai:doaj.org-article:44d3932206954187abef1a352f117c5d2021-12-02T02:25:31ZReduction of the error in the hardware neural network1818-11712312-0789https://doaj.org/article/44d3932206954187abef1a352f117c5d2007-06-01T00:00:00Zhttp://alkej.uobaghdad.edu.iq/index.php/alkej/article/view/623https://doaj.org/toc/1818-1171https://doaj.org/toc/2312-0789 Specialized hardware implementations of Artificial Neural Networks (ANNs) can offer faster execution than general-purpose microprocessors by taking advantage of reusable modules, parallel processes and specialized computational components. Modern high-density Field Programmable Gate Arrays (FPGAs) offer the required flexibility and fast design-to-implementation time with the possibility of exploiting highly parallel computations like those required by ANNs in hardware. The bounded width of the data in FPGA ANNs will add an additional error to the result of the output. This paper derives the equations of the additional error value that generate from bounded width of the data and proposed a method to reduce the effect of the error to give an optimal result in the output with a low cost. Dhafer r. ZagharAl-Khwarizmi College of Engineering – University of BaghdadarticleChemical engineeringTP155-156Engineering (General). Civil engineering (General)TA1-2040ENAl-Khawarizmi Engineering Journal, Vol 3, Iss 2 (2007)
institution	DOAJ
collection	DOAJ
language	EN
topic	Chemical engineering TP155-156 Engineering (General). Civil engineering (General) TA1-2040
spellingShingle	Chemical engineering TP155-156 Engineering (General). Civil engineering (General) TA1-2040 Dhafer r. Zaghar Reduction of the error in the hardware neural network
description	Specialized hardware implementations of Artificial Neural Networks (ANNs) can offer faster execution than general-purpose microprocessors by taking advantage of reusable modules, parallel processes and specialized computational components. Modern high-density Field Programmable Gate Arrays (FPGAs) offer the required flexibility and fast design-to-implementation time with the possibility of exploiting highly parallel computations like those required by ANNs in hardware. The bounded width of the data in FPGA ANNs will add an additional error to the result of the output. This paper derives the equations of the additional error value that generate from bounded width of the data and proposed a method to reduce the effect of the error to give an optimal result in the output with a low cost.
format	article
author	Dhafer r. Zaghar
author_facet	Dhafer r. Zaghar
author_sort	Dhafer r. Zaghar
title	Reduction of the error in the hardware neural network
title_short	Reduction of the error in the hardware neural network
title_full	Reduction of the error in the hardware neural network
title_fullStr	Reduction of the error in the hardware neural network
title_full_unstemmed	Reduction of the error in the hardware neural network
title_sort	reduction of the error in the hardware neural network
publisher	Al-Khwarizmi College of Engineering – University of Baghdad
publishDate	2007
url	https://doaj.org/article/44d3932206954187abef1a352f117c5d
work_keys_str_mv	AT dhaferrzaghar reductionoftheerrorinthehardwareneuralnetwork
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Reduction of the error in the hardware neural network

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