A Highly Efficient and Linear mm-Wave CMOS Power Amplifier Using a Compact Symmetrical Parallel–Parallel Power Combiner With IMD3 Cancellation for 5G Applications
This paper presents a fully integrated linear power amplifier (PA) in a 65-nm CMOS process for mm-wave 5G applications. The proposed linear PA employs a compact symmetrical 4-way parallel–parallel power combiner with a third-order intermodulation distortion (IMD3) cancellation method to a...
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| Autores principales: | , , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
IEEE
2021
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/4ce3024ac42c40ab8b85aa4313550afa |
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| Sumario: | This paper presents a fully integrated linear power amplifier (PA) in a 65-nm CMOS process for mm-wave 5G applications. The proposed linear PA employs a compact symmetrical 4-way parallel–parallel power combiner with a third-order intermodulation distortion (IMD3) cancellation method to achieve high linear output power with a high power-added efficiency (PAE). An on-chip 4-way parallel–parallel power combiner, which combines the output power from 8-unit PAs, is designed with a compact footprint (<inline-formula> <tex-math notation="LaTeX">$241\,\,\mu \text{m}\,\,\times 241\,\,\mu \text{m}$ </tex-math></inline-formula>). Conventional series power-combining transformer based power combiners have poor symmetrical performance for the amplitude and phase of the input impedance among unit PAs owing to the parasitic effects of the power combiners. However, the proposed parallel–parallel power combiner, which is based on parallel power-combining transformer structures, shows good symmetrical performances among unit PAs. Moreover, an IMD3 cancellation method using a parallel–parallel power combiner is proposed in this work. The proposed IMD3 cancellation method can support high-order modulation signals without increasing the complexity and reduce the dependence for digital predistortion (DPD). Consequently, the proposed linearization method obtains a high linear P<sub>OUT</sub> and PAE without DPD. The PA in 65-nm CMOS demonstrates a saturated output power (P<sub>SAT</sub>) of 23.2 dBm, a 15.9-dB power gain, a 1-dB compressed output power (<inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm {O,1dB}}$ </tex-math></inline-formula>) of 22 dBm, and a peak power-added efficiency (PAE) of 33.5% at 28 GHz. The measured error vector magnitude with 100 Msym/s of 256/512-QAM is −31.2/−32.1 dB with average output power of 18.02/17.73 dBm, average PAE of 17.6/16.1%, and adjacent channel power ratio (ACPR) of −30/−33.1 dBc without DPD. To the best of the authors’ knowledge, the proposed PA demonstrates high output power with the highest PAE performance supporting 256/512-QAM compared to the recently published fully integrated mm-wave 5G CMOS PAs. |
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