Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability
The drift region of conventional drain extended NMOS (DeNMOS_C) is engineered to reduce gate charge for high performance and to enhance avalanche ruggedness for reliability in switching applications. Reduced-surface-field (RESURF) techniques, including surface implant (P-Top), split-gate...
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| Autores principales: | , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
IEEE
2021
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/505780d9a5e64348bde0b9337d325815 |
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| Sumario: | The drift region of conventional drain extended NMOS (DeNMOS_C) is engineered to reduce gate charge for high performance and to enhance avalanche ruggedness for reliability in switching applications. Reduced-surface-field (RESURF) techniques, including surface implant (P-Top), split-gate (SG), and shallow trench isolation (STI), with an optimum doping implant of the drift region, are presented to improve the on-state safe operating area (SOA) and hot carrier stress (HCS) reliability of DeNMOS after the gate charge reduction. It is shown that under unclamped inductive switching (UIS) conditions, the avalanche ruggedness of optimized devices is improved, whereas DeNMOS_C shows high susceptibility towards thermal runaway and device failure due to electrothermal effects. Switching performance shows a reduction of up to 46% in total gate charge (<inline-formula> <tex-math notation="LaTeX">$Q_{\mathrm {g}}$ </tex-math></inline-formula>) and more than 65% in gate-to-drain coupling charge (<inline-formula> <tex-math notation="LaTeX">$Q_{\mathrm {gd}}$ </tex-math></inline-formula>). Moreover, the highest improvement achieved in switching delay is 34%. The high-frequency figure of merits such as FoM1 (<inline-formula> <tex-math notation="LaTeX">$R_{\mathrm {ON}}\times Q_{\mathrm {gd}}$ </tex-math></inline-formula>) and FoM2 (<inline-formula> <tex-math notation="LaTeX">$R_{\mathrm {ON}}\times Q_{\mathrm {g}}$ </tex-math></inline-formula>) show significant improvement of up to 65% and 35%, respectively. The tradeoff in the DC figure of merits FoM3 (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {BD}}/R_{\mathrm {ON}})$ </tex-math></inline-formula> and Baliga-FoM (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {BD}}^{2}/R_{\mathrm {ON}})$ </tex-math></inline-formula> are also analyzed. Comparative analysis of optimized DeNMOS structures indicates that split gate DeNMOS without STI shows a minimum degradation of DC performance and the most significant improvement in high-frequency performance and switching reliability. |
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