Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability

The drift region of conventional drain extended NMOS (DeNMOS_C) is engineered to reduce gate charge for high performance and to enhance avalanche ruggedness for reliability in switching applications. Reduced-surface-field (RESURF) techniques, including surface implant (P-Top), split-gate...

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Autores principales:	Shraddha Pali, Ankur Gupta
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	Drain extended NMOS (DeNMOS) figure of merit (FoM) gate charge (Qg) gate-to-drain charge (Qgd.) reduced-surface-field (RESURF) switching performance Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/505780d9a5e64348bde0b9337d325815
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spelling	oai:doaj.org-article:505780d9a5e64348bde0b9337d3258152021-11-26T00:01:41ZDesign of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability2169-353610.1109/ACCESS.2021.3128059https://doaj.org/article/505780d9a5e64348bde0b9337d3258152021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9614183/https://doaj.org/toc/2169-3536The drift region of conventional drain extended NMOS (DeNMOS_C) is engineered to reduce gate charge for high performance and to enhance avalanche ruggedness for reliability in switching applications. Reduced-surface-field (RESURF) techniques, including surface implant (P-Top), split-gate (SG), and shallow trench isolation (STI), with an optimum doping implant of the drift region, are presented to improve the on-state safe operating area (SOA) and hot carrier stress (HCS) reliability of DeNMOS after the gate charge reduction. It is shown that under unclamped inductive switching (UIS) conditions, the avalanche ruggedness of optimized devices is improved, whereas DeNMOS_C shows high susceptibility towards thermal runaway and device failure due to electrothermal effects. Switching performance shows a reduction of up to 46% in total gate charge (<inline-formula> <tex-math notation="LaTeX">$Q_{\mathrm {g}}$ </tex-math></inline-formula>) and more than 65% in gate-to-drain coupling charge (<inline-formula> <tex-math notation="LaTeX">$Q_{\mathrm {gd}}$ </tex-math></inline-formula>). Moreover, the highest improvement achieved in switching delay is 34%. The high-frequency figure of merits such as FoM1 (<inline-formula> <tex-math notation="LaTeX">$R_{\mathrm {ON}}\times Q_{\mathrm {gd}}$ </tex-math></inline-formula>) and FoM2 (<inline-formula> <tex-math notation="LaTeX">$R_{\mathrm {ON}}\times Q_{\mathrm {g}}$ </tex-math></inline-formula>) show significant improvement of up to 65% and 35%, respectively. The tradeoff in the DC figure of merits FoM3 (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {BD}}/R_{\mathrm {ON}})$ </tex-math></inline-formula> and Baliga-FoM (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {BD}}^{2}/R_{\mathrm {ON}})$ </tex-math></inline-formula> are also analyzed. Comparative analysis of optimized DeNMOS structures indicates that split gate DeNMOS without STI shows a minimum degradation of DC performance and the most significant improvement in high-frequency performance and switching reliability.Shraddha PaliAnkur GuptaIEEEarticleDrain extended NMOS (DeNMOS)figure of merit (FoM)gate charge (Qg)gate-to-drain charge (Qgd.)reduced-surface-field (RESURF)switching performanceElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Access, Vol 9, Pp 155370-155379 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Drain extended NMOS (DeNMOS) figure of merit (FoM) gate charge (Qg) gate-to-drain charge (Qgd.) reduced-surface-field (RESURF) switching performance Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	Drain extended NMOS (DeNMOS) figure of merit (FoM) gate charge (Qg) gate-to-drain charge (Qgd.) reduced-surface-field (RESURF) switching performance Electrical engineering. Electronics. Nuclear engineering TK1-9971 Shraddha Pali Ankur Gupta Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability
description	The drift region of conventional drain extended NMOS (DeNMOS_C) is engineered to reduce gate charge for high performance and to enhance avalanche ruggedness for reliability in switching applications. Reduced-surface-field (RESURF) techniques, including surface implant (P-Top), split-gate (SG), and shallow trench isolation (STI), with an optimum doping implant of the drift region, are presented to improve the on-state safe operating area (SOA) and hot carrier stress (HCS) reliability of DeNMOS after the gate charge reduction. It is shown that under unclamped inductive switching (UIS) conditions, the avalanche ruggedness of optimized devices is improved, whereas DeNMOS_C shows high susceptibility towards thermal runaway and device failure due to electrothermal effects. Switching performance shows a reduction of up to 46% in total gate charge (<inline-formula> <tex-math notation="LaTeX">$Q_{\mathrm {g}}$ </tex-math></inline-formula>) and more than 65% in gate-to-drain coupling charge (<inline-formula> <tex-math notation="LaTeX">$Q_{\mathrm {gd}}$ </tex-math></inline-formula>). Moreover, the highest improvement achieved in switching delay is 34%. The high-frequency figure of merits such as FoM1 (<inline-formula> <tex-math notation="LaTeX">$R_{\mathrm {ON}}\times Q_{\mathrm {gd}}$ </tex-math></inline-formula>) and FoM2 (<inline-formula> <tex-math notation="LaTeX">$R_{\mathrm {ON}}\times Q_{\mathrm {g}}$ </tex-math></inline-formula>) show significant improvement of up to 65% and 35%, respectively. The tradeoff in the DC figure of merits FoM3 (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {BD}}/R_{\mathrm {ON}})$ </tex-math></inline-formula> and Baliga-FoM (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {BD}}^{2}/R_{\mathrm {ON}})$ </tex-math></inline-formula> are also analyzed. Comparative analysis of optimized DeNMOS structures indicates that split gate DeNMOS without STI shows a minimum degradation of DC performance and the most significant improvement in high-frequency performance and switching reliability.
format	article
author	Shraddha Pali Ankur Gupta
author_facet	Shraddha Pali Ankur Gupta
author_sort	Shraddha Pali
title	Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability
title_short	Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability
title_full	Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability
title_fullStr	Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability
title_full_unstemmed	Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability
title_sort	design of drain-extended mos devices using resurf techniques for high switching performance and avalanche reliability
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/505780d9a5e64348bde0b9337d325815
work_keys_str_mv	AT shraddhapali designofdrainextendedmosdevicesusingresurftechniquesforhighswitchingperformanceandavalanchereliability AT ankurgupta designofdrainextendedmosdevicesusingresurftechniquesforhighswitchingperformanceandavalanchereliability
_version_	1718409966763638784

Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability

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