Multidimensional Systolic Arrays of LMS Algorithm Adaptive (FIR) Digital Filters
A multidimensional systolic arrays realization of LMS algorithm by a method of mapping regular algorithm onto processor array, are designed. They are based on appropriately selected 1-D systolic array filter that depends on the inner product sum systolic implementation. Various arrays may be derive...
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| Main Authors: | , |
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| Format: | article |
| Language: | EN |
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Al-Khwarizmi College of Engineering – University of Baghdad
2009
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| Subjects: | |
| Online Access: | https://doaj.org/article/51b068c5d8614cbc908d30bba76d1103 |
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| Summary: | A multidimensional systolic arrays realization of LMS algorithm by a method of mapping regular algorithm onto processor array, are designed. They are based on appropriately selected 1-D systolic array filter that depends on the inner product sum systolic implementation. Various arrays may be derived that exhibit a regular arrangement of the cells (processors) and local interconnection pattern, which are important for VLSI implementation. It reduces latency time and increases the throughput rate in comparison to classical 1-D systolic arrays. The 3-D multilayered array consists of 2-D layers, which are connected with each other only by edges. Such arrays for LMS-based adaptive (FIR) filter may be opposed the fundamental requirements of fast convergence rate in most adaptive filter applications.
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