Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in...

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Autores principales:	Muhammad Ovais Akhter, Najam Muhammad Amin
Formato:	article
Lenguaje:	EN
Publicado:	Hindawi Limited 2021
Materias:	Engineering (General). Civil engineering (General) TA1-2040 Mathematics QA1-939
Acceso en línea:	https://doaj.org/article/5411880381d84677a173c7f9d8958780
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spelling	oai:doaj.org-article:5411880381d84677a173c7f9d89587802021-11-29T00:56:07ZDesign and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology1563-514710.1155/2021/3364016https://doaj.org/article/5411880381d84677a173c7f9d89587802021-01-01T00:00:00Zhttp://dx.doi.org/10.1155/2021/3364016https://doaj.org/toc/1563-5147This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.Muhammad Ovais AkhterNajam Muhammad AminHindawi LimitedarticleEngineering (General). Civil engineering (General)TA1-2040MathematicsQA1-939ENMathematical Problems in Engineering, Vol 2021 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Engineering (General). Civil engineering (General) TA1-2040 Mathematics QA1-939
spellingShingle	Engineering (General). Civil engineering (General) TA1-2040 Mathematics QA1-939 Muhammad Ovais Akhter Najam Muhammad Amin Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology
description	This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.
format	article
author	Muhammad Ovais Akhter Najam Muhammad Amin
author_facet	Muhammad Ovais Akhter Najam Muhammad Amin
author_sort	Muhammad Ovais Akhter
title	Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology
title_short	Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology
title_full	Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology
title_fullStr	Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology
title_full_unstemmed	Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology
title_sort	design and optimization of 2.1 mw ulp doherty power amplifier with interstage capacitances using 65 nm cmos technology
publisher	Hindawi Limited
publishDate	2021
url	https://doaj.org/article/5411880381d84677a173c7f9d8958780
work_keys_str_mv	AT muhammadovaisakhter designandoptimizationof21mwulpdohertypoweramplifierwithinterstagecapacitancesusing65nmcmostechnology AT najammuhammadamin designandoptimizationof21mwulpdohertypoweramplifierwithinterstagecapacitancesusing65nmcmostechnology
_version_	1718407706632519680

Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

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