Multidimensional Systolic Arrays of LMS AlgorithmAdaptive (FIR) Digital Filters
A multidimensional systolic arrays realization of LMS algorithm by a method of mapping regular algorithm onto processor array, are designed. They are based on appropriately selected 1-D systolic array filter that depends on the inner product sum systolic implementation. Various arrays may be derived...
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| Autores principales: | , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
Al-Khwarizmi College of Engineering – University of Baghdad
2009
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/5529feff8a894c4caf45724bdd0f59f1 |
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| Sumario: | A multidimensional systolic arrays realization of LMS algorithm by a method of mapping regular algorithm onto processor array, are designed. They are based on appropriately selected 1-D systolic array filter that depends on the inner product sum systolic implementation. Various arrays may be derived that exhibit a regular arrangement of the cells (processors) and local interconnection pattern, which are important for VLSI implementation. It reduces latency time and increases the throughput rate in comparison to classical 1-D systolic arrays. The 3-D multilayered array consists of 2-D layers, which are connected with each other only by edges. Such arrays for LMS-based adaptive (FIR) filter may be opposed the fundamental requirements of fast convergence rate in most adaptive filter applications. |
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