Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations
In a CNN (convolutional neural network) accelerator, to reduce memory traffic and power consumption, there is a need to exploit the sparsity of activation values. Therefore, some research efforts have been paid to skip ineffectual computations (i.e., multiplications by zero). Different from previous...
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| Main Authors: | , , |
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| Format: | article |
| Language: | EN |
| Published: |
MDPI AG
2021
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| Subjects: | |
| Online Access: | https://doaj.org/article/5cf53a5820af40cca4e6ee6645d2bf4d |
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