Hardware emulation of stochastic p-bits for invertible logic
Abstract The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0’s and 1’s. A completely different paradigm is based on three-terminal stochastic units which could be called “p-bits”, where the output is a random telegraphic signal continuously...
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| Autores principales: | , , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
Nature Portfolio
2017
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/6b3f5f94e4f343d895c8eecc88bb5946 |
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| Sumario: | Abstract The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0’s and 1’s. A completely different paradigm is based on three-terminal stochastic units which could be called “p-bits”, where the output is a random telegraphic signal continuously fluctuating between 0 and 1 with a tunable mean. p-bits can be interconnected to receive weighted contributions from others in a network, and these weighted contributions can be chosen to not only solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: They provide inputs consistent to a given output along with unique outputs to a given set of inputs. The existing demonstrations of accurate invertible logic are intriguing, but will these striking properties observed in computer simulations carry over to hardware implementations? This paper uses individual micro controllers to emulate p-bits, and we present results for a 4-bit ripple carry adder with 48 p-bits and a 4-bit multiplier with 46 p-bits working in inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions. |
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