Hardware emulation of stochastic p-bits for invertible logic

Abstract The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0’s and 1’s. A completely different paradigm is based on three-terminal stochastic units which could be called “p-bits”, where the output is a random telegraphic signal continuously...

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Autores principales:	Ahmed Zeeshan Pervaiz, Lakshmi Anirudh Ghantasala, Kerem Yunus Camsari, Supriyo Datta
Formato:	article
Lenguaje:	EN
Publicado:	Nature Portfolio 2017
Materias:	Medicine R Science Q
Acceso en línea:	https://doaj.org/article/6b3f5f94e4f343d895c8eecc88bb5946
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spelling	oai:doaj.org-article:6b3f5f94e4f343d895c8eecc88bb59462021-12-02T15:06:14ZHardware emulation of stochastic p-bits for invertible logic10.1038/s41598-017-11011-82045-2322https://doaj.org/article/6b3f5f94e4f343d895c8eecc88bb59462017-09-01T00:00:00Zhttps://doi.org/10.1038/s41598-017-11011-8https://doaj.org/toc/2045-2322Abstract The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0’s and 1’s. A completely different paradigm is based on three-terminal stochastic units which could be called “p-bits”, where the output is a random telegraphic signal continuously fluctuating between 0 and 1 with a tunable mean. p-bits can be interconnected to receive weighted contributions from others in a network, and these weighted contributions can be chosen to not only solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: They provide inputs consistent to a given output along with unique outputs to a given set of inputs. The existing demonstrations of accurate invertible logic are intriguing, but will these striking properties observed in computer simulations carry over to hardware implementations? This paper uses individual micro controllers to emulate p-bits, and we present results for a 4-bit ripple carry adder with 48 p-bits and a 4-bit multiplier with 46 p-bits working in inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions.Ahmed Zeeshan PervaizLakshmi Anirudh GhantasalaKerem Yunus CamsariSupriyo DattaNature PortfolioarticleMedicineRScienceQENScientific Reports, Vol 7, Iss 1, Pp 1-13 (2017)
institution	DOAJ
collection	DOAJ
language	EN
topic	Medicine R Science Q
spellingShingle	Medicine R Science Q Ahmed Zeeshan Pervaiz Lakshmi Anirudh Ghantasala Kerem Yunus Camsari Supriyo Datta Hardware emulation of stochastic p-bits for invertible logic
description	Abstract The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0’s and 1’s. A completely different paradigm is based on three-terminal stochastic units which could be called “p-bits”, where the output is a random telegraphic signal continuously fluctuating between 0 and 1 with a tunable mean. p-bits can be interconnected to receive weighted contributions from others in a network, and these weighted contributions can be chosen to not only solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: They provide inputs consistent to a given output along with unique outputs to a given set of inputs. The existing demonstrations of accurate invertible logic are intriguing, but will these striking properties observed in computer simulations carry over to hardware implementations? This paper uses individual micro controllers to emulate p-bits, and we present results for a 4-bit ripple carry adder with 48 p-bits and a 4-bit multiplier with 46 p-bits working in inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions.
format	article
author	Ahmed Zeeshan Pervaiz Lakshmi Anirudh Ghantasala Kerem Yunus Camsari Supriyo Datta
author_facet	Ahmed Zeeshan Pervaiz Lakshmi Anirudh Ghantasala Kerem Yunus Camsari Supriyo Datta
author_sort	Ahmed Zeeshan Pervaiz
title	Hardware emulation of stochastic p-bits for invertible logic
title_short	Hardware emulation of stochastic p-bits for invertible logic
title_full	Hardware emulation of stochastic p-bits for invertible logic
title_fullStr	Hardware emulation of stochastic p-bits for invertible logic
title_full_unstemmed	Hardware emulation of stochastic p-bits for invertible logic
title_sort	hardware emulation of stochastic p-bits for invertible logic
publisher	Nature Portfolio
publishDate	2017
url	https://doaj.org/article/6b3f5f94e4f343d895c8eecc88bb5946
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_version_	1718388517059428352

Hardware emulation of stochastic p-bits for invertible logic

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