FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC

The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a s...

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Autores principales:	Miroslaw Chmiel, Robert Czerwinski, Andrzej Malcher
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	programmable logic controllers (PLC) counters IEC 61131-3 field programmable gate arrays (FPGA) function blocks central processing units (CPU) Technology T Engineering (General). Civil engineering (General) TA1-2040 Biology (General) QH301-705.5 Physics QC1-999 Chemistry QD1-999
Acceso en línea:	https://doaj.org/article/78b598c90b95431c88c62d8ff0c0a080
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id	oai:doaj.org-article:78b598c90b95431c88c62d8ff0c0a080
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spelling	oai:doaj.org-article:78b598c90b95431c88c62d8ff0c0a0802021-11-11T15:14:23ZFPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC10.3390/app1121101832076-3417https://doaj.org/article/78b598c90b95431c88c62d8ff0c0a0802021-10-01T00:00:00Zhttps://www.mdpi.com/2076-3417/11/21/10183https://doaj.org/toc/2076-3417The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a single common executing unit. These solutions are compared to each other and compared with counters realized in commercially available PLCs like Siemens SIMATIC S7 controllers. The structure of integrated hardware–software CPU with counters is presented. The paper presents how the designer can take advantage of the specific features of the FPGA devices to optimize both the utilization of resources and speed of realization of the particular blocks. Experimental results prove the high efficiency of the proposed solutions.Miroslaw ChmielRobert CzerwinskiAndrzej MalcherMDPI AGarticleprogrammable logic controllers (PLC)countersIEC 61131-3field programmable gate arrays (FPGA)function blockscentral processing units (CPU)TechnologyTEngineering (General). Civil engineering (General)TA1-2040Biology (General)QH301-705.5PhysicsQC1-999ChemistryQD1-999ENApplied Sciences, Vol 11, Iss 10183, p 10183 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	programmable logic controllers (PLC) counters IEC 61131-3 field programmable gate arrays (FPGA) function blocks central processing units (CPU) Technology T Engineering (General). Civil engineering (General) TA1-2040 Biology (General) QH301-705.5 Physics QC1-999 Chemistry QD1-999
spellingShingle	programmable logic controllers (PLC) counters IEC 61131-3 field programmable gate arrays (FPGA) function blocks central processing units (CPU) Technology T Engineering (General). Civil engineering (General) TA1-2040 Biology (General) QH301-705.5 Physics QC1-999 Chemistry QD1-999 Miroslaw Chmiel Robert Czerwinski Andrzej Malcher FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
description	The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a single common executing unit. These solutions are compared to each other and compared with counters realized in commercially available PLCs like Siemens SIMATIC S7 controllers. The structure of integrated hardware–software CPU with counters is presented. The paper presents how the designer can take advantage of the specific features of the FPGA devices to optimize both the utilization of resources and speed of realization of the particular blocks. Experimental results prove the high efficiency of the proposed solutions.
format	article
author	Miroslaw Chmiel Robert Czerwinski Andrzej Malcher
author_facet	Miroslaw Chmiel Robert Czerwinski Andrzej Malcher
author_sort	Miroslaw Chmiel
title	FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
title_short	FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
title_full	FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
title_fullStr	FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
title_full_unstemmed	FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
title_sort	fpga implementation of iec-61131-3-based hardware aided counters for plc
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/78b598c90b95431c88c62d8ff0c0a080
work_keys_str_mv	AT miroslawchmiel fpgaimplementationofiec611313basedhardwareaidedcountersforplc AT robertczerwinski fpgaimplementationofiec611313basedhardwareaidedcountersforplc AT andrzejmalcher fpgaimplementationofiec611313basedhardwareaidedcountersforplc
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FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC

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