CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions

The design of neural network architectures is carried out using methods that optimize a particular objective function, in which a point that minimizes the function is sought. In reported works, they only focused on software simulations or commercial complementary metal-oxide-semiconductor (CMOS), ne...

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Autores principales:	Alejandro Medina-Santiago, Carlos Arturo Hernández-Gracidas, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Monica Amador García, Jorge Antonio Orozco Torres
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	CMOS circuit analog system signal processing learning algorithm artificial neural network Chemical technology TP1-1185
Acceso en línea:	https://doaj.org/article/793ffac73a24459690c215081bc79033
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spelling	oai:doaj.org-article:793ffac73a24459690c215081bc790332021-11-11T19:05:23ZCMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions10.3390/s212170711424-8220https://doaj.org/article/793ffac73a24459690c215081bc790332021-10-01T00:00:00Zhttps://www.mdpi.com/1424-8220/21/21/7071https://doaj.org/toc/1424-8220The design of neural network architectures is carried out using methods that optimize a particular objective function, in which a point that minimizes the function is sought. In reported works, they only focused on software simulations or commercial complementary metal-oxide-semiconductor (CMOS), neither of which guarantees the quality of the solution. In this work, we designed a hardware architecture using individual neurons as building blocks based on the optimization of n-dimensional objective functions, such as obtaining the bias and synaptic weight parameters of an artificial neural network (ANN) model using the gradient descent method. The ANN-based architecture has a 5-3-1 configuration and is implemented on a 1.2 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>m technology integrated circuit, with a total power consumption of 46.08 mW, using nine neurons and 36 CMOS operational amplifiers (op-amps). We show the results obtained from the application of integrated circuits for ANNs simulated in PSpice applied to the classification of digital data, demonstrating that the optimization method successfully obtains the synaptic weights and bias values generated by the learning algorithm (Steepest-Descent), for the design of the neural architecture.Alejandro Medina-SantiagoCarlos Arturo Hernández-GracidasLuis Alberto Morales-RosalesIgnacio Algredo-BadilloMonica Amador GarcíaJorge Antonio Orozco TorresMDPI AGarticleCMOS circuitanalog systemsignal processinglearning algorithmartificial neural networkChemical technologyTP1-1185ENSensors, Vol 21, Iss 7071, p 7071 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	CMOS circuit analog system signal processing learning algorithm artificial neural network Chemical technology TP1-1185
spellingShingle	CMOS circuit analog system signal processing learning algorithm artificial neural network Chemical technology TP1-1185 Alejandro Medina-Santiago Carlos Arturo Hernández-Gracidas Luis Alberto Morales-Rosales Ignacio Algredo-Badillo Monica Amador García Jorge Antonio Orozco Torres CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions
description	The design of neural network architectures is carried out using methods that optimize a particular objective function, in which a point that minimizes the function is sought. In reported works, they only focused on software simulations or commercial complementary metal-oxide-semiconductor (CMOS), neither of which guarantees the quality of the solution. In this work, we designed a hardware architecture using individual neurons as building blocks based on the optimization of n-dimensional objective functions, such as obtaining the bias and synaptic weight parameters of an artificial neural network (ANN) model using the gradient descent method. The ANN-based architecture has a 5-3-1 configuration and is implemented on a 1.2 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>m technology integrated circuit, with a total power consumption of 46.08 mW, using nine neurons and 36 CMOS operational amplifiers (op-amps). We show the results obtained from the application of integrated circuits for ANNs simulated in PSpice applied to the classification of digital data, demonstrating that the optimization method successfully obtains the synaptic weights and bias values generated by the learning algorithm (Steepest-Descent), for the design of the neural architecture.
format	article
author	Alejandro Medina-Santiago Carlos Arturo Hernández-Gracidas Luis Alberto Morales-Rosales Ignacio Algredo-Badillo Monica Amador García Jorge Antonio Orozco Torres
author_facet	Alejandro Medina-Santiago Carlos Arturo Hernández-Gracidas Luis Alberto Morales-Rosales Ignacio Algredo-Badillo Monica Amador García Jorge Antonio Orozco Torres
author_sort	Alejandro Medina-Santiago
title	CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions
title_short	CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions
title_full	CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions
title_fullStr	CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions
title_full_unstemmed	CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions
title_sort	cmos implementation of anns based on analog optimization of n-dimensional objective functions
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/793ffac73a24459690c215081bc79033
work_keys_str_mv	AT alejandromedinasantiago cmosimplementationofannsbasedonanalogoptimizationofndimensionalobjectivefunctions AT carlosarturohernandezgracidas cmosimplementationofannsbasedonanalogoptimizationofndimensionalobjectivefunctions AT luisalbertomoralesrosales cmosimplementationofannsbasedonanalogoptimizationofndimensionalobjectivefunctions AT ignacioalgredobadillo cmosimplementationofannsbasedonanalogoptimizationofndimensionalobjectivefunctions AT monicaamadorgarcia cmosimplementationofannsbasedonanalogoptimizationofndimensionalobjectivefunctions AT jorgeantonioorozcotorres cmosimplementationofannsbasedonanalogoptimizationofndimensionalobjectivefunctions
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CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions

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