LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms

The Open Radio Access Network (RAN) concept has been gaining wide acceptance in recent network architectures, including 5G New Radio (NR) network deployments. Current Open RAN radio implementation efforts, aim at integrating several white-box hardware elements and executing digital processing on ope...

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Autores principales:	Elissaios Alexios Papatheofanous, Dionysios Reisis, Konstantinos Nikitopoulos
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	5G New Radio (5G NR) accelerator field-programmable gate array (FPGA) low density parity check (LDPC) radio access network (RAN) Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/7bcf9d7f5dcc469b9665d6080a800ab6
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id	oai:doaj.org-article:7bcf9d7f5dcc469b9665d6080a800ab6
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spelling	oai:doaj.org-article:7bcf9d7f5dcc469b9665d6080a800ab62021-11-20T00:01:56ZLDPC Hardware Acceleration in 5G Open Radio Access Network Platforms2169-353610.1109/ACCESS.2021.3127039https://doaj.org/article/7bcf9d7f5dcc469b9665d6080a800ab62021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9610039/https://doaj.org/toc/2169-3536The Open Radio Access Network (RAN) concept has been gaining wide acceptance in recent network architectures, including 5G New Radio (NR) network deployments. Current Open RAN radio implementation efforts, aim at integrating several white-box hardware elements and executing digital processing on open-source software. When building such a software-based, 5G Open RAN platform, challenges include achieving real-time execution times for demanding computational blocks of the 5G NR physical layer processing, such as Low Density Parity Check (LDPC) decoding. In this context, having already identified both the capabilities as well as the challenges that Field-programmable Gate Arrays (FPGAs) offer for accelerating LDPC, we present our novel LDPC FPGA accelerator system. In this paper, we contribute the implementation details of our FPGA accelerator design as well as the process of integrating the accelerator with OpenAirInterface (OAI), the basis for our 5G NR platform. For the first time in the literature, we show an FPGA-based LDPC accelerator fully integrated with a complete software platform, that is able to achieve more than <inline-formula> <tex-math notation="LaTeX">$1.6Gbps$ </tex-math></inline-formula> decoding throughput and up to 13 times faster execution times compared to single core software implementations. Finally, in our results, we show that LDPC encoding is more challenging to accelerate due to lower computational complexity.Elissaios Alexios PapatheofanousDionysios ReisisKonstantinos NikitopoulosIEEEarticle5G New Radio (5G NR)acceleratorfield-programmable gate array (FPGA)low density parity check (LDPC)radio access network (RAN)Electrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Access, Vol 9, Pp 152960-152971 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	5G New Radio (5G NR) accelerator field-programmable gate array (FPGA) low density parity check (LDPC) radio access network (RAN) Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	5G New Radio (5G NR) accelerator field-programmable gate array (FPGA) low density parity check (LDPC) radio access network (RAN) Electrical engineering. Electronics. Nuclear engineering TK1-9971 Elissaios Alexios Papatheofanous Dionysios Reisis Konstantinos Nikitopoulos LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms
description	The Open Radio Access Network (RAN) concept has been gaining wide acceptance in recent network architectures, including 5G New Radio (NR) network deployments. Current Open RAN radio implementation efforts, aim at integrating several white-box hardware elements and executing digital processing on open-source software. When building such a software-based, 5G Open RAN platform, challenges include achieving real-time execution times for demanding computational blocks of the 5G NR physical layer processing, such as Low Density Parity Check (LDPC) decoding. In this context, having already identified both the capabilities as well as the challenges that Field-programmable Gate Arrays (FPGAs) offer for accelerating LDPC, we present our novel LDPC FPGA accelerator system. In this paper, we contribute the implementation details of our FPGA accelerator design as well as the process of integrating the accelerator with OpenAirInterface (OAI), the basis for our 5G NR platform. For the first time in the literature, we show an FPGA-based LDPC accelerator fully integrated with a complete software platform, that is able to achieve more than <inline-formula> <tex-math notation="LaTeX">$1.6Gbps$ </tex-math></inline-formula> decoding throughput and up to 13 times faster execution times compared to single core software implementations. Finally, in our results, we show that LDPC encoding is more challenging to accelerate due to lower computational complexity.
format	article
author	Elissaios Alexios Papatheofanous Dionysios Reisis Konstantinos Nikitopoulos
author_facet	Elissaios Alexios Papatheofanous Dionysios Reisis Konstantinos Nikitopoulos
author_sort	Elissaios Alexios Papatheofanous
title	LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms
title_short	LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms
title_full	LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms
title_fullStr	LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms
title_full_unstemmed	LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms
title_sort	ldpc hardware acceleration in 5g open radio access network platforms
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/7bcf9d7f5dcc469b9665d6080a800ab6
work_keys_str_mv	AT elissaiosalexiospapatheofanous ldpchardwareaccelerationin5gopenradioaccessnetworkplatforms AT dionysiosreisis ldpchardwareaccelerationin5gopenradioaccessnetworkplatforms AT konstantinosnikitopoulos ldpchardwareaccelerationin5gopenradioaccessnetworkplatforms
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LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms

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