Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory
In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better packing density, have been dramatically increas...
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MDPI AG
2021
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oai:doaj.org-article:7d81118ead744c04afee6966bb63ae602021-11-25T18:22:54ZDielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory10.3390/mi121112972072-666Xhttps://doaj.org/article/7d81118ead744c04afee6966bb63ae602021-10-01T00:00:00Zhttps://www.mdpi.com/2072-666X/12/11/1297https://doaj.org/toc/2072-666XIn contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better packing density, have been dramatically increased under limited height of NAND string. In this context, finding a novel approach based on dielectric engineering seems timely and applicable. This paper covers the voltage interference characteristics in 3D NAND with respect to dielectrics, then proposes an alternative cell structure to suppress such interference.Woo-Jin JungJun-Young ParkMDPI AGarticledielectricsflash memoryinterferencecell-programmingvacuum dielectricV-NANDMechanical engineering and machineryTJ1-1570ENMicromachines, Vol 12, Iss 1297, p 1297 (2021) |
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DOAJ |
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dielectrics flash memory interference cell-programming vacuum dielectric V-NAND Mechanical engineering and machinery TJ1-1570 |
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dielectrics flash memory interference cell-programming vacuum dielectric V-NAND Mechanical engineering and machinery TJ1-1570 Woo-Jin Jung Jun-Young Park Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory |
description |
In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better packing density, have been dramatically increased under limited height of NAND string. In this context, finding a novel approach based on dielectric engineering seems timely and applicable. This paper covers the voltage interference characteristics in 3D NAND with respect to dielectrics, then proposes an alternative cell structure to suppress such interference. |
format |
article |
author |
Woo-Jin Jung Jun-Young Park |
author_facet |
Woo-Jin Jung Jun-Young Park |
author_sort |
Woo-Jin Jung |
title |
Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory |
title_short |
Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory |
title_full |
Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory |
title_fullStr |
Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory |
title_full_unstemmed |
Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory |
title_sort |
dielectric engineering to suppress cell-to-cell programming voltage interference in 3d nand flash memory |
publisher |
MDPI AG |
publishDate |
2021 |
url |
https://doaj.org/article/7d81118ead744c04afee6966bb63ae60 |
work_keys_str_mv |
AT woojinjung dielectricengineeringtosuppresscelltocellprogrammingvoltageinterferencein3dnandflashmemory AT junyoungpark dielectricengineeringtosuppresscelltocellprogrammingvoltageinterferencein3dnandflashmemory |
_version_ |
1718411268089446400 |