Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM
In order to cope with the storage wall of the von Neumann computing architecture, the computing in-memory (CIM) architecture embeds logic in the memory, and completes the operation while reading the data, so that the storage unit has computing power and reduces processing data transfer between the d...
Guardado en:
| Autor principal: | |
|---|---|
| Formato: | article |
| Lenguaje: | ZH |
| Publicado: |
Journal of Computer Engineering and Applications Beijing Co., Ltd., Science Press
2021
|
| Materias: | |
| Acceso en línea: | https://doaj.org/article/8079443d52f2411c9b270ccb595a8bb5 |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
| Sumario: | In order to cope with the storage wall of the von Neumann computing architecture, the computing in-memory (CIM) architecture embeds logic in the memory, and completes the operation while reading the data, so that the storage unit has computing power and reduces processing data transfer between the device and the memory. In order to realize the design of large-capacity and low-cost memory, this paper proposes a storage system based on 4T SRAM (static random access memory) with double word line and double threshold, which can not only realize data storage and reading, but also realize BCAM (binary content addressable memory) operations and logic operations such as AND, NOR, and XOR. During logic operation, two rows of storage data are selected through the decoding circuit, the bit lines are all pre-discharged to a low level, and the bit line voltage is compared with the reference voltage through the bit line end sensitive amplifier and the operation result is output. During BCAM operation, the external input data are decoded by the decoding circuit to realize the on and off control of the left and right transmission tubes of the storage unit, and the bit line end sensitive amplifier outputs the matching result through the NOR gate. The proposed circuit is built and simulated under 65 nm CMOS technology. Compared with the 6T memory cell, the storage area of the 4T memory cell is reduced by 25%. Compared with the single word line 4T memory structure, the double word line 4T memory structure can save about 47% of the read power consumption in very large scale integration (VLSI) applications. The maximum power consumption of data matching during BCAM operation is 909.72 FJ, and the array operation speed of N columns can reach 16161.6×N MB/Hz when the word line voltage is 600 mV. |
|---|