Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM

In order to cope with the storage wall of the von Neumann computing architecture, the computing in-memory (CIM) architecture embeds logic in the memory, and completes the operation while reading the data, so that the storage unit has computing power and reduces processing data transfer between the d...

Descripción completa

Guardado en:

Detalles Bibliográficos
Autor principal:	LIN Zhiting, NIU Jianchao+, WU Xiulong, PENG Chunyu
Formato:	article
Lenguaje:	ZH
Publicado:	Journal of Computer Engineering and Applications Beijing Co., Ltd., Science Press 2021
Materias:	computing in-memory (cim) binary content addressable memory (bcam) 4t sram Electronic computers. Computer science QA75.5-76.95
Acceso en línea:	https://doaj.org/article/8079443d52f2411c9b270ccb595a8bb5
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

id	oai:doaj.org-article:8079443d52f2411c9b270ccb595a8bb5
record_format	dspace
spelling	oai:doaj.org-article:8079443d52f2411c9b270ccb595a8bb52021-11-10T08:10:58ZComputing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM10.3778/j.issn.1673-9418.20110901673-9418https://doaj.org/article/8079443d52f2411c9b270ccb595a8bb52021-11-01T00:00:00Zhttp://fcst.ceaj.org/CN/abstract/abstract2951.shtmlhttps://doaj.org/toc/1673-9418In order to cope with the storage wall of the von Neumann computing architecture, the computing in-memory (CIM) architecture embeds logic in the memory, and completes the operation while reading the data, so that the storage unit has computing power and reduces processing data transfer between the device and the memory. In order to realize the design of large-capacity and low-cost memory, this paper proposes a storage system based on 4T SRAM (static random access memory) with double word line and double threshold, which can not only realize data storage and reading, but also realize BCAM (binary content addressable memory) operations and logic operations such as AND, NOR, and XOR. During logic operation, two rows of storage data are selected through the decoding circuit, the bit lines are all pre-discharged to a low level, and the bit line voltage is compared with the reference voltage through the bit line end sensitive amplifier and the operation result is output. During BCAM operation, the external input data are decoded by the decoding circuit to realize the on and off control of the left and right transmission tubes of the storage unit, and the bit line end sensitive amplifier outputs the matching result through the NOR gate. The proposed circuit is built and simulated under 65 nm CMOS technology. Compared with the 6T memory cell, the storage area of the 4T memory cell is reduced by 25%. Compared with the single word line 4T memory structure, the double word line 4T memory structure can save about 47% of the read power consumption in very large scale integration (VLSI) applications. The maximum power consumption of data matching during BCAM operation is 909.72 FJ, and the array operation speed of N columns can reach 16161.6×N MB/Hz when the word line voltage is 600 mV.LIN Zhiting, NIU Jianchao+, WU Xiulong, PENG ChunyuJournal of Computer Engineering and Applications Beijing Co., Ltd., Science Pressarticlecomputing in-memory (cim)binary content addressable memory (bcam)4t sramElectronic computers. Computer scienceQA75.5-76.95ZHJisuanji kexue yu tansuo, Vol 15, Iss 11, Pp 2116-2126 (2021)
institution	DOAJ
collection	DOAJ
language	ZH
topic	computing in-memory (cim) binary content addressable memory (bcam) 4t sram Electronic computers. Computer science QA75.5-76.95
spellingShingle	computing in-memory (cim) binary content addressable memory (bcam) 4t sram Electronic computers. Computer science QA75.5-76.95 LIN Zhiting, NIU Jianchao+, WU Xiulong, PENG Chunyu Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM
description	In order to cope with the storage wall of the von Neumann computing architecture, the computing in-memory (CIM) architecture embeds logic in the memory, and completes the operation while reading the data, so that the storage unit has computing power and reduces processing data transfer between the device and the memory. In order to realize the design of large-capacity and low-cost memory, this paper proposes a storage system based on 4T SRAM (static random access memory) with double word line and double threshold, which can not only realize data storage and reading, but also realize BCAM (binary content addressable memory) operations and logic operations such as AND, NOR, and XOR. During logic operation, two rows of storage data are selected through the decoding circuit, the bit lines are all pre-discharged to a low level, and the bit line voltage is compared with the reference voltage through the bit line end sensitive amplifier and the operation result is output. During BCAM operation, the external input data are decoded by the decoding circuit to realize the on and off control of the left and right transmission tubes of the storage unit, and the bit line end sensitive amplifier outputs the matching result through the NOR gate. The proposed circuit is built and simulated under 65 nm CMOS technology. Compared with the 6T memory cell, the storage area of the 4T memory cell is reduced by 25%. Compared with the single word line 4T memory structure, the double word line 4T memory structure can save about 47% of the read power consumption in very large scale integration (VLSI) applications. The maximum power consumption of data matching during BCAM operation is 909.72 FJ, and the array operation speed of N columns can reach 16161.6×N MB/Hz when the word line voltage is 600 mV.
format	article
author	LIN Zhiting, NIU Jianchao+, WU Xiulong, PENG Chunyu
author_facet	LIN Zhiting, NIU Jianchao+, WU Xiulong, PENG Chunyu
author_sort	LIN Zhiting, NIU Jianchao+, WU Xiulong, PENG Chunyu
title	Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM
title_short	Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM
title_full	Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM
title_fullStr	Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM
title_full_unstemmed	Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM
title_sort	computing in-memory design based on double word line and double threshold 4t sram
publisher	Journal of Computer Engineering and Applications Beijing Co., Ltd., Science Press
publishDate	2021
url	https://doaj.org/article/8079443d52f2411c9b270ccb595a8bb5
work_keys_str_mv	AT linzhitingniujianchaowuxiulongpengchunyu computinginmemorydesignbasedondoublewordlineanddoublethreshold4tsram
_version_	1718440390601736192

Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM

Ejemplares similares