Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA

Time-domain back-projection (BP) is a widely known method used in synthetic aperture radar (SAR) image formation. Despite its advantages over other image formation algorithms, the BP method is hindered due to its computational complexity and its requirement of higher number of operations and process...

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Autores principales:	Don Lahiru Nirmal Hettiarachchi, Eric J. Balster
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	Back-projection field-programmable gate array (FPGA) hardware acceleration high-level synthesis (HLS) Intel Stratix 10 OpenCL Ocean engineering TC1501-1800 Geophysics. Cosmic physics QC801-809
Acceso en línea:	https://doaj.org/article/828f0358407f4b58a933895add09f817
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id	oai:doaj.org-article:828f0358407f4b58a933895add09f817
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spelling	oai:doaj.org-article:828f0358407f4b58a933895add09f8172021-11-18T00:00:28ZFixed-Point Processing of the SAR Back-Projection Algorithm on FPGA2151-153510.1109/JSTARS.2021.3119007https://doaj.org/article/828f0358407f4b58a933895add09f8172021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9566797/https://doaj.org/toc/2151-1535Time-domain back-projection (BP) is a widely known method used in synthetic aperture radar (SAR) image formation. Despite its advantages over other image formation algorithms, the BP method is hindered due to its computational complexity and its requirement of higher number of operations and processing power. Recently, field-programmable gate array (FPGA) devices have been used for BP acceleration mainly due to their parallel processing capabilities, reconfigurability, scalability, and low power requirement. This article presents a new fixed-point based BP (FxBP) design for FPGA devices and a floating-point-based BP (FlBP) design to compare performance. Both designs are developed with <italic>N</italic>-dimensional range (NDR) structure and single-work item (SWI) structure using OpenCL. The FPGA performance is evaluated using an FPGA performance metric. It is shown that FxBP-NDR and FxBP-SWI designs generate high-quality back-projected images compared to FlBP designs, while saving 16.87% and 42.54% on logic resources and gaining 17.90% and 91.62% on FPGA performance in NDR and SWI, respectively. Obtained results clearly indicate that FPGA devices perform significantly better with FxBP designs compared to FlBP designs, even with hardened FPUs.Don Lahiru Nirmal HettiarachchiEric J. BalsterIEEEarticleBack-projectionfield-programmable gate array (FPGA)hardware accelerationhigh-level synthesis (HLS)Intel Stratix 10OpenCLOcean engineeringTC1501-1800Geophysics. Cosmic physicsQC801-809ENIEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing, Vol 14, Pp 10889-10902 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Back-projection field-programmable gate array (FPGA) hardware acceleration high-level synthesis (HLS) Intel Stratix 10 OpenCL Ocean engineering TC1501-1800 Geophysics. Cosmic physics QC801-809
spellingShingle	Back-projection field-programmable gate array (FPGA) hardware acceleration high-level synthesis (HLS) Intel Stratix 10 OpenCL Ocean engineering TC1501-1800 Geophysics. Cosmic physics QC801-809 Don Lahiru Nirmal Hettiarachchi Eric J. Balster Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA
description	Time-domain back-projection (BP) is a widely known method used in synthetic aperture radar (SAR) image formation. Despite its advantages over other image formation algorithms, the BP method is hindered due to its computational complexity and its requirement of higher number of operations and processing power. Recently, field-programmable gate array (FPGA) devices have been used for BP acceleration mainly due to their parallel processing capabilities, reconfigurability, scalability, and low power requirement. This article presents a new fixed-point based BP (FxBP) design for FPGA devices and a floating-point-based BP (FlBP) design to compare performance. Both designs are developed with <italic>N</italic>-dimensional range (NDR) structure and single-work item (SWI) structure using OpenCL. The FPGA performance is evaluated using an FPGA performance metric. It is shown that FxBP-NDR and FxBP-SWI designs generate high-quality back-projected images compared to FlBP designs, while saving 16.87% and 42.54% on logic resources and gaining 17.90% and 91.62% on FPGA performance in NDR and SWI, respectively. Obtained results clearly indicate that FPGA devices perform significantly better with FxBP designs compared to FlBP designs, even with hardened FPUs.
format	article
author	Don Lahiru Nirmal Hettiarachchi Eric J. Balster
author_facet	Don Lahiru Nirmal Hettiarachchi Eric J. Balster
author_sort	Don Lahiru Nirmal Hettiarachchi
title	Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA
title_short	Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA
title_full	Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA
title_fullStr	Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA
title_full_unstemmed	Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA
title_sort	fixed-point processing of the sar back-projection algorithm on fpga
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/828f0358407f4b58a933895add09f817
work_keys_str_mv	AT donlahirunirmalhettiarachchi fixedpointprocessingofthesarbackprojectionalgorithmonfpga AT ericjbalster fixedpointprocessingofthesarbackprojectionalgorithmonfpga
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Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA

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