Design of 10T SRAM cell with improved read performance and expanded write margin

Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters t...

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Autores principales:	Ashish Sachdeva, V. K. Tomar
Formato:	article
Lenguaje:	EN
Publicado:	Wiley 2021
Materias:	Computer engineering. Computer hardware TK7885-7895
Acceso en línea:	https://doaj.org/article/89c3b594cf4c469d96fc8de6a893508d
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spelling	oai:doaj.org-article:89c3b594cf4c469d96fc8de6a893508d2021-11-06T03:20:48ZDesign of 10T SRAM cell with improved read performance and expanded write margin1751-85981751-858X10.1049/cds2.12006https://doaj.org/article/89c3b594cf4c469d96fc8de6a893508d2021-01-01T00:00:00Zhttps://doi.org/10.1049/cds2.12006https://doaj.org/toc/1751-858Xhttps://doaj.org/toc/1751-8598Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.Ashish SachdevaV. K. TomarWileyarticleComputer engineering. Computer hardwareTK7885-7895ENIET Circuits, Devices and Systems, Vol 15, Iss 1, Pp 42-64 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Computer engineering. Computer hardware TK7885-7895
spellingShingle	Computer engineering. Computer hardware TK7885-7895 Ashish Sachdeva V. K. Tomar Design of 10T SRAM cell with improved read performance and expanded write margin
description	Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.
format	article
author	Ashish Sachdeva V. K. Tomar
author_facet	Ashish Sachdeva V. K. Tomar
author_sort	Ashish Sachdeva
title	Design of 10T SRAM cell with improved read performance and expanded write margin
title_short	Design of 10T SRAM cell with improved read performance and expanded write margin
title_full	Design of 10T SRAM cell with improved read performance and expanded write margin
title_fullStr	Design of 10T SRAM cell with improved read performance and expanded write margin
title_full_unstemmed	Design of 10T SRAM cell with improved read performance and expanded write margin
title_sort	design of 10t sram cell with improved read performance and expanded write margin
publisher	Wiley
publishDate	2021
url	https://doaj.org/article/89c3b594cf4c469d96fc8de6a893508d
work_keys_str_mv	AT ashishsachdeva designof10tsramcellwithimprovedreadperformanceandexpandedwritemargin AT vktomar designof10tsramcellwithimprovedreadperformanceandexpandedwritemargin
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Design of 10T SRAM cell with improved read performance and expanded write margin

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