Effect of HfO<sub>2</sub>-Based Multi-Dielectrics on Electrical Properties of Amorphous In-Ga-Zn-O Thin Film Transistors
We report the fabrication of bottom gate a-IGZO TFTs based on HfO<sub>2</sub> stacked dielectrics with decent electrical characteristics and bias stability. The microscopic, electrical, and optical properties of room temperature deposited a-IGZO film with varied oxygen content were explo...
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| Autores principales: | , , , , , , , , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
MDPI AG
2021
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/939dc7e05e9c4b57aacc3df576f81f19 |
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| Sumario: | We report the fabrication of bottom gate a-IGZO TFTs based on HfO<sub>2</sub> stacked dielectrics with decent electrical characteristics and bias stability. The microscopic, electrical, and optical properties of room temperature deposited a-IGZO film with varied oxygen content were explored. In order to suppress the bulk defects in the HfO<sub>2</sub> thin film and hence maximize the quality, surface modification of the SiN<sub>x</sub> film was investigated so as to achieve a more uniform layer. The root mean square (RMS) roughness of SiN<sub>x</sub>/HfO<sub>2</sub>/SiN<sub>x</sub> (SHS) stacked dielectrics was only 0.66 nm, which was reduced by 35% compared with HfO<sub>2</sub> single film (1.04 nm). The basic electrical characteristics of SHS-based a-IGZO TFT were as follows: <i>V</i><sub>th</sub> is 2.4 V, <i>μ</i><sub>sat</sub> is 21.1 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>, <i>I</i><sub>on</sub>/<i>I</i><sub>off</sub> of 3.3 × 10<sup>7</sup>, <i>I</i><sub>off</sub> is 10<sup>−11</sup> A, and <i>SS</i> is 0.22 V/dec. Zr-doped HfO<sub>2</sub> could form a more stable surface, which will decrease the bulk defect states so that the stability of device can be improved. It was found that the electrical characteristics were improved after Zr doping, with a <i>V</i><sub>th</sub> of 1.4 V, <i>I</i><sub>on</sub>/<i>I</i><sub>off</sub> of 10<sup>8</sup>, <i>μ</i><sub>sat</sub> of 19.5 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>, <i>I</i><sub>off</sub> of 10<sup>−12</sup> A, <i>SS</i> of 0.18 V/dec. After positive gate bias stress of 10<sup>4</sup> s, the Δ<i>V</i><sub>th</sub> was decreased from 0.43 V (without Zr doping) to 0.09 V (with Zr doping), the Δ<i>SS</i> was decreased from 0.19 V/dec to 0.057 V/dec, respectively, which shows a meaningful impact to realize the long-term working stability of TFT devices. |
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