A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS

A 10 Gb/s PAM-4 transmitter (TX) with a modulo-based equalization technique is presented. The proposed feed-forward Tomlinson-Harashima precoding (FF-THP) scheme takes advantage of both Tomlinson-Harashima precoding (THP) and feed-forward equalization (FFE). The vertical eye margin (VEM) is enhanced...

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Autores principales: Byungjun Kang, Gyu-Seob Jeong, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Hyojun Kim, Han-Gon Ko, Moon-Chul Choi, Deog-Kyoon Jeong
Formato: article
Lenguaje:EN
Publicado: IEEE 2021
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Acceso en línea:https://doaj.org/article/a1222b27a2534eafae53be7a52e01438
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Sumario:A 10 Gb/s PAM-4 transmitter (TX) with a modulo-based equalization technique is presented. The proposed feed-forward Tomlinson-Harashima precoding (FF-THP) scheme takes advantage of both Tomlinson-Harashima precoding (THP) and feed-forward equalization (FFE). The vertical eye margin (VEM) is enhanced by removing the precursor inter-symbol interference (ISI) with pretaps while incorporating the modulo operation. The VEMs of equalization methods are derived based on z-domain response (ZDR). The effectiveness of the FF-THP is examined by quantitative analysis and numerical simulation. Especially for a one-pole channel with a precursor, optimized tap coefficients of an FFE and an FF-THP are derived as closed-form concerning the precursor and the first postcursor. Calculations of decision threshold voltage and estimated bathtub curve based on Gaussian noise are featured by using the histogram of an eye diagram. The advantages of the FF-THP over a conventional FFE are measured by a fabricated chip. The proposed TX compensates for a 21 dB channel loss with a level mismatch ratio of 99.1&#x0025; and with a figure of merit (energy efficiency per sum of channel ISI) of 4.05 pJ/b/ISI. Moreover, the FF-THP achieves 38&#x0025; and 87.5&#x0025; improvement on VEM and horizontal eye margin, respectively, compared with an FFE. It is fabricated in 28 nm CMOS technology, occupying an active area of 0.075 mm<sup>2</sup>.