Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input
This paper presents the asynchronous digital low-dropout regulator (AD-LDO) with dual adjustment mode in ultra-low voltage input. The architecture of the proposed AD-LDO consists of the asynchronous control loop and the power PMOS array. The proposed AD-LDO is controlled by switched bidirectional as...
Guardado en:
Autores principales: | , , , |
---|---|
Formato: | article |
Lenguaje: | EN |
Publicado: |
IEEE
2021
|
Materias: | |
Acceso en línea: | https://doaj.org/article/a23ca686c12e4d8880efe48c43f7a7be |
Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
id |
oai:doaj.org-article:a23ca686c12e4d8880efe48c43f7a7be |
---|---|
record_format |
dspace |
spelling |
oai:doaj.org-article:a23ca686c12e4d8880efe48c43f7a7be2021-12-03T00:00:51ZAsynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input2169-353610.1109/ACCESS.2021.3128948https://doaj.org/article/a23ca686c12e4d8880efe48c43f7a7be2021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9618933/https://doaj.org/toc/2169-3536This paper presents the asynchronous digital low-dropout regulator (AD-LDO) with dual adjustment mode in ultra-low voltage input. The architecture of the proposed AD-LDO consists of the asynchronous control loop and the power PMOS array. The proposed AD-LDO is controlled by switched bidirectional asynchronous control loop which can eliminate the clock power consumption of synchronous LDO. The dual adjustment mode can not only provide wider loading current, but also can reduce output voltage ripple. Moreover, the proposed AD-LDO only uses one bidirectional asynchronous control loop for two adjustment modes, so it can save area and reduce power consumption. Under the 350mV input voltage and 300mV output voltage, the proposed AD-LDO can provide 2.4mA output current with 99.8% current efficiency and only consume <inline-formula> <tex-math notation="LaTeX">$5~\mu \text{A}$ </tex-math></inline-formula> quiescent current. Therefore, the proposed LDO is suitable for applications of wearable electronic devices with an ultra-low supply voltage.Wei-Bin YangChi-Hsuan SunDiptendu Sinha RoyYi-Mei ChenIEEEarticleAsynchronous digital low-dropout regulatorasynchronous control loopultra-low voltagedual adjustment modewearable electronic devicesElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Access, Vol 9, Pp 157563-157570 (2021) |
institution |
DOAJ |
collection |
DOAJ |
language |
EN |
topic |
Asynchronous digital low-dropout regulator asynchronous control loop ultra-low voltage dual adjustment mode wearable electronic devices Electrical engineering. Electronics. Nuclear engineering TK1-9971 |
spellingShingle |
Asynchronous digital low-dropout regulator asynchronous control loop ultra-low voltage dual adjustment mode wearable electronic devices Electrical engineering. Electronics. Nuclear engineering TK1-9971 Wei-Bin Yang Chi-Hsuan Sun Diptendu Sinha Roy Yi-Mei Chen Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input |
description |
This paper presents the asynchronous digital low-dropout regulator (AD-LDO) with dual adjustment mode in ultra-low voltage input. The architecture of the proposed AD-LDO consists of the asynchronous control loop and the power PMOS array. The proposed AD-LDO is controlled by switched bidirectional asynchronous control loop which can eliminate the clock power consumption of synchronous LDO. The dual adjustment mode can not only provide wider loading current, but also can reduce output voltage ripple. Moreover, the proposed AD-LDO only uses one bidirectional asynchronous control loop for two adjustment modes, so it can save area and reduce power consumption. Under the 350mV input voltage and 300mV output voltage, the proposed AD-LDO can provide 2.4mA output current with 99.8% current efficiency and only consume <inline-formula> <tex-math notation="LaTeX">$5~\mu \text{A}$ </tex-math></inline-formula> quiescent current. Therefore, the proposed LDO is suitable for applications of wearable electronic devices with an ultra-low supply voltage. |
format |
article |
author |
Wei-Bin Yang Chi-Hsuan Sun Diptendu Sinha Roy Yi-Mei Chen |
author_facet |
Wei-Bin Yang Chi-Hsuan Sun Diptendu Sinha Roy Yi-Mei Chen |
author_sort |
Wei-Bin Yang |
title |
Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input |
title_short |
Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input |
title_full |
Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input |
title_fullStr |
Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input |
title_full_unstemmed |
Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input |
title_sort |
asynchronous digital low-dropout regulator with dual adjustment mode in ultra-low voltage input |
publisher |
IEEE |
publishDate |
2021 |
url |
https://doaj.org/article/a23ca686c12e4d8880efe48c43f7a7be |
work_keys_str_mv |
AT weibinyang asynchronousdigitallowdropoutregulatorwithdualadjustmentmodeinultralowvoltageinput AT chihsuansun asynchronousdigitallowdropoutregulatorwithdualadjustmentmodeinultralowvoltageinput AT diptendusinharoy asynchronousdigitallowdropoutregulatorwithdualadjustmentmodeinultralowvoltageinput AT yimeichen asynchronousdigitallowdropoutregulatorwithdualadjustmentmodeinultralowvoltageinput |
_version_ |
1718374005614837760 |