A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

Abstract The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research report...

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Autores principales:	Jérôme K. Folla, Maria L. Crespo, Evariste T. Wembe, Mohammad A. S. Bhuiyan, Andres Cicuttin, Bernard Z. Essimbi, Mamun B. I. Reaz
Formato:	article
Lenguaje:	EN
Publicado:	Wiley 2021
Materias:	Computer engineering. Computer hardware TK7885-7895
Acceso en línea:	https://doaj.org/article/a943c9e5961042da96b09e89c39d3a92
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spelling	oai:doaj.org-article:a943c9e5961042da96b09e89c39d3a922021-11-06T03:20:47ZA low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage1751-85981751-858X10.1049/cds2.12008https://doaj.org/article/a943c9e5961042da96b09e89c39d3a922021-01-01T00:00:00Zhttps://doi.org/10.1049/cds2.12008https://doaj.org/toc/1751-858Xhttps://doaj.org/toc/1751-8598Abstract The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low‐offset, low‐power and high‐speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans‐conductance of the cross‐coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm2.Jérôme K. FollaMaria L. CrespoEvariste T. WembeMohammad A. S. BhuiyanAndres CicuttinBernard Z. EssimbiMamun B. I. ReazWileyarticleComputer engineering. Computer hardwareTK7885-7895ENIET Circuits, Devices and Systems, Vol 15, Iss 1, Pp 65-77 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Computer engineering. Computer hardware TK7885-7895
spellingShingle	Computer engineering. Computer hardware TK7885-7895 Jérôme K. Folla Maria L. Crespo Evariste T. Wembe Mohammad A. S. Bhuiyan Andres Cicuttin Bernard Z. Essimbi Mamun B. I. Reaz A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage
description	Abstract The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low‐offset, low‐power and high‐speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans‐conductance of the cross‐coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm2.
format	article
author	Jérôme K. Folla Maria L. Crespo Evariste T. Wembe Mohammad A. S. Bhuiyan Andres Cicuttin Bernard Z. Essimbi Mamun B. I. Reaz
author_facet	Jérôme K. Folla Maria L. Crespo Evariste T. Wembe Mohammad A. S. Bhuiyan Andres Cicuttin Bernard Z. Essimbi Mamun B. I. Reaz
author_sort	Jérôme K. Folla
title	A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage
title_short	A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage
title_full	A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage
title_fullStr	A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage
title_full_unstemmed	A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage
title_sort	low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage
publisher	Wiley
publishDate	2021
url	https://doaj.org/article/a943c9e5961042da96b09e89c39d3a92
work_keys_str_mv	AT jeromekfolla alowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT marialcrespo alowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT evaristetwembe alowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT mohammadasbhuiyan alowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT andrescicuttin alowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT bernardzessimbi alowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT mamunbireaz alowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT jeromekfolla lowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT marialcrespo lowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT evaristetwembe lowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT mohammadasbhuiyan lowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT andrescicuttin lowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT bernardzessimbi lowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage AT mamunbireaz lowoffsetlowpowerandhighspeeddynamiclatchcomparatorwithapreamplifierenhancedstage
_version_	1718443935036080128

A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

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