Dendritic hold and read: a gated mechanism for short term information storage and retrieval.
Two contrasting theories have been proposed to explain the mechanistic basis of short term memory. One theory posits that short term memory is represented by persistent neural activity supported by reverberating feedback networks. An alternate, more recent theory posits that short term memory can be...
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| Autores principales: | , , , , , , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
Public Library of Science (PLoS)
2012
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/a950364a8180441fbbec45d5619980b9 |
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| Sumario: | Two contrasting theories have been proposed to explain the mechanistic basis of short term memory. One theory posits that short term memory is represented by persistent neural activity supported by reverberating feedback networks. An alternate, more recent theory posits that short term memory can be supported by feedforward networks. While feedback driven memory can be implemented by well described mechanisms of synaptic plasticity, little is known of possible molecular and cellular mechanisms that can implement feedforward driven memory. Here we report such a mechanism in which the memory trace exists in the form of glutamate-bound but Mg(2+)-blocked NMDA receptors on the thin terminal dendrites of CA1 pyramidal neurons. Because glutamate dissociates from subsets of NMDA receptors very slowly, excitatory synaptic transmission can leave a silent residual trace that outlasts the electrical activity by hundreds of milliseconds. Read-out of the memory trace is possible if a critical level of these bound-but-blocked receptors accumulates on a dendritic branch that will allow these quasi-stable receptors to sustain a regenerative depolarization when triggered by an independent gating signal. This process is referred to here as dendritic hold and read (DHR). Because the read-out of the input is not dependent on repetition of the input and information flows in a single-pass manner, DHR can potentially support a feedforward memory architecture. |
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