A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator

Abstract The moduli 2n multiplier plays a vital role in the design of a residue number system processor. When the radix‐8 booth‐encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. This paper presents an area and...

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Autores principales: Naveen Kr. Kabra, Zuber M. Patel
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Lenguaje:EN
Publicado: Wiley 2021
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Acceso en línea:https://doaj.org/article/b1b6d78d0ed54cf09049608f94eba939
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spelling oai:doaj.org-article:b1b6d78d0ed54cf09049608f94eba9392021-11-17T13:28:44ZA radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator1751-861X1751-860110.1049/cdt2.12001https://doaj.org/article/b1b6d78d0ed54cf09049608f94eba9392021-01-01T00:00:00Zhttps://doi.org/10.1049/cdt2.12001https://doaj.org/toc/1751-8601https://doaj.org/toc/1751-861XAbstract The moduli 2n multiplier plays a vital role in the design of a residue number system processor. When the radix‐8 booth‐encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. This paper presents an area and power optimization technique for this kind of generators and its implementation in modulo 2n multiplier to improve the performance. The proposed hard multiplier generator (HMG) uses only ⌈log2n⌉‐2 prefix levels and (n−6)⌈log2n⌉−(⌈log2n⌉−1)2⌈log2n⌉2 total prefix operators. The synthesis of the proposed architectures is done using the Cadence tool at Generic Process design Kit‐45 nm technology. The post‐synthesis result of HMG shows 20.27%–36.57%, 2.43%–18.41% saving in area and power, respectively, while the post‐layout result of HMG shows 20.01%–35.26% and 1.33%–29.44% saving in area and power, respectively. The post‐layout result of modulo 2nmultiplier using optimized HMG shows 7.88%–10.04%, 7.87%–12.50%, 3.09%–11.29%, and 3.11%–8.79% saving in area, power, switching energy and Area delay product, respectively.Naveen Kr. KabraZuber M. PatelWileyarticleComputer engineering. Computer hardwareTK7885-7895Electronic computers. Computer scienceQA75.5-76.95ENIET Computers & Digital Techniques, Vol 15, Iss 1, Pp 36-55 (2021)
institution DOAJ
collection DOAJ
language EN
topic Computer engineering. Computer hardware
TK7885-7895
Electronic computers. Computer science
QA75.5-76.95
spellingShingle Computer engineering. Computer hardware
TK7885-7895
Electronic computers. Computer science
QA75.5-76.95
Naveen Kr. Kabra
Zuber M. Patel
A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator
description Abstract The moduli 2n multiplier plays a vital role in the design of a residue number system processor. When the radix‐8 booth‐encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. This paper presents an area and power optimization technique for this kind of generators and its implementation in modulo 2n multiplier to improve the performance. The proposed hard multiplier generator (HMG) uses only ⌈log2n⌉‐2 prefix levels and (n−6)⌈log2n⌉−(⌈log2n⌉−1)2⌈log2n⌉2 total prefix operators. The synthesis of the proposed architectures is done using the Cadence tool at Generic Process design Kit‐45 nm technology. The post‐synthesis result of HMG shows 20.27%–36.57%, 2.43%–18.41% saving in area and power, respectively, while the post‐layout result of HMG shows 20.01%–35.26% and 1.33%–29.44% saving in area and power, respectively. The post‐layout result of modulo 2nmultiplier using optimized HMG shows 7.88%–10.04%, 7.87%–12.50%, 3.09%–11.29%, and 3.11%–8.79% saving in area, power, switching energy and Area delay product, respectively.
format article
author Naveen Kr. Kabra
Zuber M. Patel
author_facet Naveen Kr. Kabra
Zuber M. Patel
author_sort Naveen Kr. Kabra
title A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator
title_short A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator
title_full A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator
title_fullStr A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator
title_full_unstemmed A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator
title_sort radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator
publisher Wiley
publishDate 2021
url https://doaj.org/article/b1b6d78d0ed54cf09049608f94eba939
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AT naveenkrkabra radix8modulo2nmultiplierusingareaandpoweroptimizedhardmultiplegenerator
AT zubermpatel radix8modulo2nmultiplierusingareaandpoweroptimizedhardmultiplegenerator
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