Design & Implementation of High Switching & Low Phase Noise Frequency Synthesizer
This research describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = -92dBc & spurious -100 dBc The deve...
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| Formato: | article |
| Lenguaje: | EN |
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Al-Khwarizmi College of Engineering – University of Baghdad
2017
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| Acceso en línea: | https://doaj.org/article/b62528662bac41ecafdf37a0cf462afe |
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| Sumario: | This research describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = -92dBc & spurious -100 dBc
The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar & reference divider in single chip. Therefore our system consists of a single chip contains (low phase noise PFD, charge pump, prescalar & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The single chip is used to provide the following properties :
Low power consumption.
Small size, light weight.
Flexibility in selecting crystal oscillator frequencies to fit into the system frequency planning.
High reliability.
The application of this synthesizer in frequency hopping systems, satellite communications & radar because it has high switching speed ,low phase noise & low spurious level.
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