A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and...

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Autores principales:	Fang Tang, Qiyun Ma, Zhou Shu, Yuanjin Zheng, Amine Bermak
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	SAR ADC high linearity low power switching procedure Electronics TK7800-8360
Acceso en línea:	https://doaj.org/article/b856adeba7734de080e05538ab72e3f8
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spelling	oai:doaj.org-article:b856adeba7734de080e05538ab72e3f82021-11-25T17:25:22ZA 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme10.3390/electronics102228562079-9292https://doaj.org/article/b856adeba7734de080e05538ab72e3f82021-11-01T00:00:00Zhttps://www.mdpi.com/2079-9292/10/22/2856https://doaj.org/toc/2079-9292This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mrow></mrow><mn>2</mn></msup></semantics></math></inline-formula>. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.Fang TangQiyun MaZhou ShuYuanjin ZhengAmine BermakMDPI AGarticleSARADChigh linearitylow powerswitching procedureElectronicsTK7800-8360ENElectronics, Vol 10, Iss 2856, p 2856 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	SAR ADC high linearity low power switching procedure Electronics TK7800-8360
spellingShingle	SAR ADC high linearity low power switching procedure Electronics TK7800-8360 Fang Tang Qiyun Ma Zhou Shu Yuanjin Zheng Amine Bermak A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme
description	This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mrow></mrow><mn>2</mn></msup></semantics></math></inline-formula>. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.
format	article
author	Fang Tang Qiyun Ma Zhou Shu Yuanjin Zheng Amine Bermak
author_facet	Fang Tang Qiyun Ma Zhou Shu Yuanjin Zheng Amine Bermak
author_sort	Fang Tang
title	A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme
title_short	A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme
title_full	A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme
title_fullStr	A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme
title_full_unstemmed	A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme
title_sort	28 nm cmos 10 bit 100 ms/s asynchronous sar adc with low-power switching procedure and timing-protection scheme
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/b856adeba7734de080e05538ab72e3f8
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A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

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