A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and...

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Autores principales: Fang Tang, Qiyun Ma, Zhou Shu, Yuanjin Zheng, Amine Bermak
Formato: article
Lenguaje:EN
Publicado: MDPI AG 2021
Materias:
SAR
ADC
high linearity
low power
switching procedure
Electronics
TK7800-8360
Acceso en línea:https://doaj.org/article/b856adeba7734de080e05538ab72e3f8
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https://doaj.org/article/b856adeba7734de080e05538ab72e3f8

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