Embedding delay‐based physical unclonable functions in networks‐on‐chip

Abstract Physical unclonable functions (PUFs) are emerging as security primitives by exploiting the intrinsic device features in various hardware security solutions. This article proposes a mechanism to embed delay‐based PUFs, namely arbiter PUF and ring‐oscillator PUF, in the network‐on‐chip (NoC)...

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Autores principales:	Prasad Nagabhushanamgari, Vikash Sehwag, Indrajit Chakrabarti, Santanu Chattopadhyay
Formato:	article
Lenguaje:	EN
Publicado:	Wiley 2021
Materias:	Computer engineering. Computer hardware TK7885-7895
Acceso en línea:	https://doaj.org/article/b8ac1a606c044f6ba6e5914c7ed46dfe
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spelling	oai:doaj.org-article:b8ac1a606c044f6ba6e5914c7ed46dfe2021-11-06T03:20:47ZEmbedding delay‐based physical unclonable functions in networks‐on‐chip1751-85981751-858X10.1049/cds2.12004https://doaj.org/article/b8ac1a606c044f6ba6e5914c7ed46dfe2021-01-01T00:00:00Zhttps://doi.org/10.1049/cds2.12004https://doaj.org/toc/1751-858Xhttps://doaj.org/toc/1751-8598Abstract Physical unclonable functions (PUFs) are emerging as security primitives by exploiting the intrinsic device features in various hardware security solutions. This article proposes a mechanism to embed delay‐based PUFs, namely arbiter PUF and ring‐oscillator PUF, in the network‐on‐chip (NoC) architecture. These embedded PUFs are constructed by reusing already available hardware resources in NoCs, such as the crossbar switches. Pass transistors, which work as control components, have been added into the delay paths. A 5‐port NoC router has been considered and the corresponding 5 × 5 crossbar switches have been analysed after obtaining a suitable layout to embed the delay‐based PUFs. The embedded PUFs have been qualitatively analysed for their robustness against variations in supply‐voltage. Furthermore, a qualitative study on generating secret keys from the embedded PUFs has been presented. A PUF‐specific layout has been considered for implementing the NoC crossbar switches, and for extracting the RC interconnection delays. Monte Carlo simulations have been performed to evaluate the quality metrics of the proposed embedded PUFs for a 64‐bit response. Area overheads incurred for realizing the proposed embedded PUFs have been found to be 6.38% and 2.68%, for arbiter PUF and ring‐oscillator PUF, respectively. Furthermore, by incorporating the pass transistors in the control components, the reliability metrics have been found to be reasonably improved over traditional constructions of the arbiter and the ring‐oscillator PUFs.Prasad NagabhushanamgariVikash SehwagIndrajit ChakrabartiSantanu ChattopadhyayWileyarticleComputer engineering. Computer hardwareTK7885-7895ENIET Circuits, Devices and Systems, Vol 15, Iss 1, Pp 27-41 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Computer engineering. Computer hardware TK7885-7895
spellingShingle	Computer engineering. Computer hardware TK7885-7895 Prasad Nagabhushanamgari Vikash Sehwag Indrajit Chakrabarti Santanu Chattopadhyay Embedding delay‐based physical unclonable functions in networks‐on‐chip
description	Abstract Physical unclonable functions (PUFs) are emerging as security primitives by exploiting the intrinsic device features in various hardware security solutions. This article proposes a mechanism to embed delay‐based PUFs, namely arbiter PUF and ring‐oscillator PUF, in the network‐on‐chip (NoC) architecture. These embedded PUFs are constructed by reusing already available hardware resources in NoCs, such as the crossbar switches. Pass transistors, which work as control components, have been added into the delay paths. A 5‐port NoC router has been considered and the corresponding 5 × 5 crossbar switches have been analysed after obtaining a suitable layout to embed the delay‐based PUFs. The embedded PUFs have been qualitatively analysed for their robustness against variations in supply‐voltage. Furthermore, a qualitative study on generating secret keys from the embedded PUFs has been presented. A PUF‐specific layout has been considered for implementing the NoC crossbar switches, and for extracting the RC interconnection delays. Monte Carlo simulations have been performed to evaluate the quality metrics of the proposed embedded PUFs for a 64‐bit response. Area overheads incurred for realizing the proposed embedded PUFs have been found to be 6.38% and 2.68%, for arbiter PUF and ring‐oscillator PUF, respectively. Furthermore, by incorporating the pass transistors in the control components, the reliability metrics have been found to be reasonably improved over traditional constructions of the arbiter and the ring‐oscillator PUFs.
format	article
author	Prasad Nagabhushanamgari Vikash Sehwag Indrajit Chakrabarti Santanu Chattopadhyay
author_facet	Prasad Nagabhushanamgari Vikash Sehwag Indrajit Chakrabarti Santanu Chattopadhyay
author_sort	Prasad Nagabhushanamgari
title	Embedding delay‐based physical unclonable functions in networks‐on‐chip
title_short	Embedding delay‐based physical unclonable functions in networks‐on‐chip
title_full	Embedding delay‐based physical unclonable functions in networks‐on‐chip
title_fullStr	Embedding delay‐based physical unclonable functions in networks‐on‐chip
title_full_unstemmed	Embedding delay‐based physical unclonable functions in networks‐on‐chip
title_sort	embedding delay‐based physical unclonable functions in networks‐on‐chip
publisher	Wiley
publishDate	2021
url	https://doaj.org/article/b8ac1a606c044f6ba6e5914c7ed46dfe
work_keys_str_mv	AT prasadnagabhushanamgari embeddingdelaybasedphysicalunclonablefunctionsinnetworksonchip AT vikashsehwag embeddingdelaybasedphysicalunclonablefunctionsinnetworksonchip AT indrajitchakrabarti embeddingdelaybasedphysicalunclonablefunctionsinnetworksonchip AT santanuchattopadhyay embeddingdelaybasedphysicalunclonablefunctionsinnetworksonchip
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Embedding delay‐based physical unclonable functions in networks‐on‐chip

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