A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>...

Descripción completa

Guardado en:
Detalles Bibliográficos
Autores principales: Muhammad Rashid, Mohammad Mazyad Hazzazi, Sikandar Zulqarnain Khan, Adel R. Alharbi, Asher Sajid, Amer Aljaedi
Formato: article
Lenguaje:EN
Publicado: MDPI AG 2021
Materias:
elliptic-curve cryptography
point multiplication
hardware architecture
FPGA
Electronics
TK7800-8360
Acceso en línea:https://doaj.org/article/b97e7b65edd54319b13a8d39866ac902
Etiquetas: Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
id oai:doaj.org-article:b97e7b65edd54319b13a8d39866ac902
record_format dspace
spelling oai:doaj.org-article:b97e7b65edd54319b13a8d39866ac9022021-11-11T15:41:30ZA Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography10.3390/electronics102126982079-9292https://doaj.org/article/b97e7b65edd54319b13a8d39866ac9022021-11-01T00:00:00Zhttps://www.mdpi.com/2079-9292/10/21/2698https://doaj.org/toc/2079-9292This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula> with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula> is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W) and Kintex-7 (61 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.Muhammad RashidMohammad Mazyad HazzaziSikandar Zulqarnain KhanAdel R. AlharbiAsher SajidAmer AljaediMDPI AGarticleelliptic-curve cryptographypoint multiplicationhardware architectureFPGAElectronicsTK7800-8360ENElectronics, Vol 10, Iss 2698, p 2698 (2021)
institution DOAJ
collection DOAJ
language EN
topic elliptic-curve cryptography
point multiplication
hardware architecture
FPGA
Electronics
TK7800-8360
spellingShingle elliptic-curve cryptography
point multiplication
hardware architecture
FPGA
Electronics
TK7800-8360
Muhammad Rashid
Mohammad Mazyad Hazzazi
Sikandar Zulqarnain Khan
Adel R. Alharbi
Asher Sajid
Amer Aljaedi
A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography
description This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula> with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula> is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W) and Kintex-7 (61 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.
format article
author Muhammad Rashid
Mohammad Mazyad Hazzazi
Sikandar Zulqarnain Khan
Adel R. Alharbi
Asher Sajid
Amer Aljaedi
author_facet Muhammad Rashid
Mohammad Mazyad Hazzazi
Sikandar Zulqarnain Khan
Adel R. Alharbi
Asher Sajid
Amer Aljaedi
author_sort Muhammad Rashid
title A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography
title_short A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography
title_full A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography
title_fullStr A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography
title_full_unstemmed A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography
title_sort novel low-area point multiplication architecture for elliptic-curve cryptography
publisher MDPI AG
publishDate 2021
url https://doaj.org/article/b97e7b65edd54319b13a8d39866ac902
work_keys_str_mv AT muhammadrashid anovellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT mohammadmazyadhazzazi anovellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT sikandarzulqarnainkhan anovellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT adelralharbi anovellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT ashersajid anovellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT ameraljaedi anovellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT muhammadrashid novellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT mohammadmazyadhazzazi novellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT sikandarzulqarnainkhan novellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT adelralharbi novellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT ashersajid novellowareapointmultiplicationarchitectureforellipticcurvecryptography
AT ameraljaedi novellowareapointmultiplicationarchitectureforellipticcurvecryptography
_version_ 1718434242041479168

Ejemplares similares