Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications. This article explores the connection between the physical structure of a device-level silicon controlled rectifier (SCR) and high-fai...

Descripción completa

Guardado en:

Detalles Bibliográficos
Autores principales:	Yang Wang, Xiangliang Jin, Yan Peng, Jun Luo, Zeyu Zhong, Jun Yang
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2020
Materias:	CMOS process CMOS technology electron devices Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/c25fca2cf82d4c759b04bbbec80ebe52
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

id	oai:doaj.org-article:c25fca2cf82d4c759b04bbbec80ebe52
record_format	dspace
spelling	oai:doaj.org-article:c25fca2cf82d4c759b04bbbec80ebe522021-11-19T00:04:52ZAnalysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection2169-353610.1109/ACCESS.2020.3042313https://doaj.org/article/c25fca2cf82d4c759b04bbbec80ebe522020-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9279212/https://doaj.org/toc/2169-3536As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications. This article explores the connection between the physical structure of a device-level silicon controlled rectifier (SCR) and high-failure ESD characteristics. The gate-controlled silicon controlled rectifier (GCSCR) based on the gate control effect is fabricated using the <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> standard bipolar complementary-metal-oxide-semiconductor double-diffused-metal-oxide-semiconductor (BCD) process. The ESD characteristics of the device are analyzed by technology computer aided design (TCAD) simulation and equivalent circuits. The transmission line pulse (TLP) is used to test the performance of the device. The results show that when the gate length is <inline-formula> <tex-math notation="LaTeX">$4~\mu \text{m}$ </tex-math></inline-formula>, the failure current of the device is only 1.56A. When the gate length is <inline-formula> <tex-math notation="LaTeX">$1~\mu \text{m}$ </tex-math></inline-formula>, the trigger voltage and the holding voltage of the device are 24.4V and 21.1V respectively, and the failure current is 34.94A. According to the test results of the above devices, it can be concluded that the current release mode of GCSCR with different gate sizes significantly affects the ESD characteristics of the device.Yang WangXiangliang JinYan PengJun LuoZeyu ZhongJun YangIEEEarticleCMOS processCMOS technologyelectron devicesElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Access, Vol 8, Pp 217213-217221 (2020)
institution	DOAJ
collection	DOAJ
language	EN
topic	CMOS process CMOS technology electron devices Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	CMOS process CMOS technology electron devices Electrical engineering. Electronics. Nuclear engineering TK1-9971 Yang Wang Xiangliang Jin Yan Peng Jun Luo Zeyu Zhong Jun Yang Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection
description	As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications. This article explores the connection between the physical structure of a device-level silicon controlled rectifier (SCR) and high-failure ESD characteristics. The gate-controlled silicon controlled rectifier (GCSCR) based on the gate control effect is fabricated using the <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> standard bipolar complementary-metal-oxide-semiconductor double-diffused-metal-oxide-semiconductor (BCD) process. The ESD characteristics of the device are analyzed by technology computer aided design (TCAD) simulation and equivalent circuits. The transmission line pulse (TLP) is used to test the performance of the device. The results show that when the gate length is <inline-formula> <tex-math notation="LaTeX">$4~\mu \text{m}$ </tex-math></inline-formula>, the failure current of the device is only 1.56A. When the gate length is <inline-formula> <tex-math notation="LaTeX">$1~\mu \text{m}$ </tex-math></inline-formula>, the trigger voltage and the holding voltage of the device are 24.4V and 21.1V respectively, and the failure current is 34.94A. According to the test results of the above devices, it can be concluded that the current release mode of GCSCR with different gate sizes significantly affects the ESD characteristics of the device.
format	article
author	Yang Wang Xiangliang Jin Yan Peng Jun Luo Zeyu Zhong Jun Yang
author_facet	Yang Wang Xiangliang Jin Yan Peng Jun Luo Zeyu Zhong Jun Yang
author_sort	Yang Wang
title	Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection
title_short	Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection
title_full	Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection
title_fullStr	Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection
title_full_unstemmed	Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection
title_sort	analysis of high-failure mechanism based on gate-controlled device for electro-static discharge protection
publisher	IEEE
publishDate	2020
url	https://doaj.org/article/c25fca2cf82d4c759b04bbbec80ebe52
work_keys_str_mv	AT yangwang analysisofhighfailuremechanismbasedongatecontrolleddeviceforelectrostaticdischargeprotection AT xiangliangjin analysisofhighfailuremechanismbasedongatecontrolleddeviceforelectrostaticdischargeprotection AT yanpeng analysisofhighfailuremechanismbasedongatecontrolleddeviceforelectrostaticdischargeprotection AT junluo analysisofhighfailuremechanismbasedongatecontrolleddeviceforelectrostaticdischargeprotection AT zeyuzhong analysisofhighfailuremechanismbasedongatecontrolleddeviceforelectrostaticdischargeprotection AT junyang analysisofhighfailuremechanismbasedongatecontrolleddeviceforelectrostaticdischargeprotection
_version_	1718420692317241344

Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

Ejemplares similares