Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection
As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications. This article explores the connection between the physical structure of a device-level silicon controlled rectifier (SCR) and high-fai...
Guardado en:
| Autores principales: | , , , , , |
|---|---|
| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
IEEE
2020
|
| Materias: | |
| Acceso en línea: | https://doaj.org/article/c25fca2cf82d4c759b04bbbec80ebe52 |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Sea el primero en dejar un comentario!