An X-Band CMOS Digital Phased Array Radar from Hardware to Software

Phased array technology features rapid and directional scanning and has become a promising approach for remote sensing and wireless communication. In addition, element-level digitization has increased the feasibility of complicated signal processing and simultaneous multi-beamforming processes. Howe...

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Autores principales: Yue-Ming Wu, Hao-Chung Chou, Cheng-Yung Ke, Chien-Cheng Wang, Chien-Te Li, Li-Han Chang, Borching Su, Ta-Shun Chu, Yu-Jiu Wang
Formato: article
Lenguaje:EN
Publicado: MDPI AG 2021
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Acceso en línea:https://doaj.org/article/c2e08ea043f44a87bab3e6e992238a97
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Sumario:Phased array technology features rapid and directional scanning and has become a promising approach for remote sensing and wireless communication. In addition, element-level digitization has increased the feasibility of complicated signal processing and simultaneous multi-beamforming processes. However, the high cost and bulky characteristics of beam-steering systems have prevented their extensive application. In this paper, an X-band element-level digital phased array radar utilizing fully integrated complementary metal-oxide-semiconductor (CMOS) transceivers is proposed for achieving a low-cost and compact-size digital beamforming system. An 8–10 GHz transceiver system-on-chip (SoC) fabricated in 65 nm CMOS technology offers baseband filtering, frequency translation, and global clock synchronization through the proposed periodic pulse injection technique. A 16-element subarray module with an SoC integration, antenna-in-package, and tile array configuration achieves digital beamforming, back-end computing, and dc–dc conversion with a size of 317 × 149 × 74.6 mm<sup>3</sup>. A radar demonstrator with scalable subarray modules simultaneously realizes range sensing and azimuth recognition for pulsed radar configurations. Captured by the suggested software-defined pulsed radar, a complete range–azimuth figure with a 1 km maximum observation range can be displayed within 150 ms under the current implementation.