An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking

An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking

This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, the n...

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Detalles Bibliográficos
Autores principales: Muhammad Riaz Ur Rehman, Arash Hejazi, Imran Ali, Muhammad Asif, Seongjin Oh, Pervesh Kumar, Younggun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Yeonjae Jung, Hyungki Huh, Seokkee Kim, Joon-Mo Yoo, Kang-Yoon Lee
Formato: article
Lenguaje:EN
Publicado: IEEE 2021
Materias:
ADPLL
injection locked frequency multiplier
low power
small area
Internet of Things
digitally-controlled oscillator
Electrical engineering. Electronics. Nuclear engineering
TK1-9971
Acceso en línea:https://doaj.org/article/c9ac4dc344304972b4c5c288c7a90f58
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Sumario:This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, the need for Time-to-Digital Converter (TDC) is eliminated through providing the CFTL circuitry. This feature makes the design compact, low power, and suitable for IoT applications. The proposed design is based on a synthesizable pulse injection and frequency-locked loop along with an ultra-low-power LC Digitally-Controlled Oscillator (LC-DCO). The presented CFTL circuit adjusts the frequency of the DCO continuously and prevents the frequency drift after the reference injection. Inside the designed LC-DCO core, the power consumption is minimized by optimizing the <inline-formula> <tex-math notation="LaTeX">$\text{g}_{\mathrm {m}}~/\text{I}_{\mathrm {D}}$ </tex-math></inline-formula> and adjusting the power supply to 0.5 V. The proposed ILFM based ADPLL is fabricated in 55 nm CMOS technology and covers the operational frequency range of 2.402 GHz to 2.480 GHz with a reference frequency of 32 MHz. The measured phase noise performance of the ADPLL is &#x2212;111.15 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.4 GHz. It consumes only 0.46 mW power with an active area of 0.129 mm<sup>2</sup>.

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